參數資料
型號: CAT25128YI-GT2
廠商: ON SEMICONDUCTOR
元件分類: PROM
英文描述: 16K X 8 SPI BUS SERIAL EEPROM, PDSO8
封裝: 4.40 X 3 MM, HALOGEN FREE AND ROHS COMPLIANT, MO-153, TSSOP-8
文件頁數: 10/16頁
文件大小: 172K
代理商: CAT25128YI-GT2
CAT25128
http://onsemi.com
3
Table 5. A.C. CHARACTERISTICS (TA = 40°C to +85°C (Industrial) and TA = 40°C to +125°C (Extended).) (Notes 4, 7)
Symbol
Parameter
VCC = 1.8 V 5.5 V / 405C to +855C
VCC = 2.5 V 5.5 V / 405C to +1255C
VCC = 2.5 V 5.5 V
405C to +855C
Units
Min
Max
Min
Max
fSCK
Clock Frequency
DC
5
DC
10
MHz
tSU
Data Setup Time
40
20
ns
tH
Data Hold Time
40
20
ns
tWH
SCK High Time
75
40
ns
tWL
SCK Low Time
75
40
ns
tLZ
HOLD to Output Low Z
50
25
ns
tRI (Note 5)
Input Rise Time
2
ms
tFI (Note 5)
Input Fall Time
2
ms
tHD
HOLD Setup Time
0
ns
tCD
HOLD Hold Time
10
ns
tV
Output Valid from Clock Low
75
40
ns
tHO
Output Hold Time
0
ns
tDIS
Output Disable Time
50
20
ns
tHZ
HOLD to Output High Z
100
25
ns
tCS
CS High Time
140
70
ns
tCSS
CS Setup Time
30
15
ns
tCSH
CS Hold Time
30
15
ns
tCNS
CS Inactive Setup Time
20
15
ns
tCNH
CS Inactive Hold Time
20
15
ns
tWPS
WP Setup Time
10
ns
tWPH
WP Hold Time
100
60
ns
tWC (Note 6)
Write Cycle Time
5
ms
4. AC Test Conditions:
Input Pulse Voltages: 0.3 VCC to 0.7 VCC
Input rise and fall times: ≤ 10 ns
Input and output reference voltages: 0.5 VCC
Output load: current source IOL max/IOH max; CL = 50 pF
5. This parameter is tested initially and after a design or process change that affects the parameter.
6. tWC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
7. All Chip Select (CS) timing parameters are defined relative to the positive clock edge (Figure 2). tCSH timing specification is valid
for die revision D and higher. The die revision D is identified by letter “D” or a dedicated marking code on top of the package. For
previous product revision (Rev.C) the tCSH is defined relative to the negative clock edge.
Table 6. POWERUP TIMING (Notes 5, 8)
Symbol
Parameter
Max
Units
tPUR
Powerup to Read Operation
1
ms
tPUW
Powerup to Write Operation
1
ms
8. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
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