- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄223524 > CAT25C16VA-TE13 2K X 8 SPI BUS SERIAL EEPROM, PDSO8 PDF資料下載
參數(shù)資料
| 型號： | CAT25C16VA-TE13 |
| 元件分類： | PROM |
| 英文描述： | 2K X 8 SPI BUS SERIAL EEPROM, PDSO8 |
| 封裝： | LEAD FREE AND HALOGEN FREE, SOIC-8 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 77K |
| 代理商： | CAT25C16VA-TE13 |
7
CAT25C01/02/04/08/16
Doc. No. 1016, Rev. N
Figure 4. Read Instruction Timing
Note: Dashed Line= mode (1, 1) – – – –
SK
SI
SO
0000
X*
01
1
BYTE ADDRESS*
0123456789
10
20
21
22
23
24
25
26
27
28
29
30
7
6
5
4
3
2
1
0
*Please check the Byte Address Table.
CS
OPCODE
DATA OUT
MSB
HIGH IMPEDANCE
**
AN
A0
*X = 0 for CAT25C01, CAT25C02, CAT25C08 and CAT25C16; X = A8 for CAT25C04
bits and the WPEN bit) and the block protected sections
in the memory array when the chip is hardware write
protected. Only the sections of the memory array that
are not block protected can be written. Hardware write
protection is disabled when either
WP pin is high or the
WPEN bit is zero.
DEVICE OPERATION
Write Enable and Disable
The CAT25C01/02/04/08/16 contains a write enable
latch. This latch must be set before any write operation.
The device powers up in a write disable state when Vcc
is applied. WREN instruction will enable writes (set the
latch) to the device. WRDI instruction will disable
writes(reset the latch) to the device. Disabling writes will
protect the device against inadvertent writes.
READ Sequence
The part is selected by pulling
CS low. The 8-bit read
instruction is transmitted to the CAT25C01/02/04/08/16,
followed by the 16-bit address for 25C08/16. (only 10-bit
addresses are used for 25C08, 11-bit addresses are
used for 25C16. The rest of the bits are don't care bits)
and 8-bit address for 25C01/02/04 (for the 25C04, bit 3
of the read data instruction contains address A8).
After the correct read instruction and address are sent,
the data stored in the memory at the selected address is
shifted out on the SO pin. The data stored in the memory
at the next address can be read sequentially by continu-
ing to provide clock pulses. The internal address pointer
is automatically incremented to the next higher address
after each byte of data is shifted out. When the highest
address is reached, the address counter rolls over to
0000h allowing the read cycle to be continued indefi-
nitely. The read operation is terminated by pulling the
CS
high. To read the status register, RDSR instruction
should be sent. The contents of the status register are
shifted out on the SO line. The status register may be
read at any time even during a write cycle.
Read
sequece is illustrated in Figure 4. Reading status register
is illustrated in Figure 5.
WRITE Sequence
The CAT25C01/02/04/08/16 powers up in a Write Dis-
able state. Prior to any write instructions, the WREN
instruction must be sent to CAT25C01/02/04/08/16.
The device goes into Write enable state by pulling the
CS low and then clocking the WREN instruction into
CAT25C01/02/04/08/16. The
CS must be brought high
after the WREN instruction to enable writes to the
device. If the write operation is initiated immediately after
the WREN instruction without
CS being brought high,
the data will not be written to the array because the write
enable latch will not have been properly set. Also, for a
successful write operation the address of the memory
location(s) to be programmed must be outside the
protected address field location selected by the block
protection level.
相關PDF資料 |
PDF描述 |
|---|---|
| CAT28C64BJI15 | 8K X 8 EEPROM 5V, 150 ns, PDSO28 |
| CAT28LV65JA-15T | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| CAT28LV65JA-20T | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| CAT28LV65JA-25T | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| CAT28LV65JI-15T | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CAT25C16VI | 功能描述:電可擦除可編程只讀存儲器 (2048x8) 16K RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT25C16VI-G | 功能描述:電可擦除可編程只讀存儲器 (2048x8) 16K 2.5-5.5 RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT25C16Y | 功能描述:電可擦除可編程只讀存儲器 (2048x8) 16K RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT25C16Y-1.8 | 功能描述:電可擦除可編程只讀存儲器 (2048x8) 16K RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| CAT25C16Y14 | 功能描述:電可擦除可編程只讀存儲器 (2048x8) 16K RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
發(fā)布緊急采購，3分鐘左右您將得到回復。