參數(shù)資料
型號: CAT25C16VA-TE13
元件分類: PROM
英文描述: 2K X 8 SPI BUS SERIAL EEPROM, PDSO8
封裝: LEAD FREE AND HALOGEN FREE, SOIC-8
文件頁數(shù): 8/12頁
文件大小: 77K
代理商: CAT25C16VA-TE13
5
CAT25C01/02/04/08/16
Doc. No. 1016, Rev. N
Status Register Bits
Array Address
Protection
BP1
BP0
Protected
0
None
No Protection
0
1
25C01: 60-7F
Quarter Array Protection
25C02: C0-FF
25C04: 180-1FF
25C08: 0300-03FF
25C16: 0600-07FF
1
0
25C01: 40-7F
Half Array Protection
25C02: 80-FF
25C04: 100-1FF
25C08: 0200-03FF
25C16: 0400-07FF
1
25C01: 00-7F
Full Array Protection
25C02: 00-FF
25C04: 000-1FF
25C08: 0000-03FF
25C16: 0000-07FF
BLOCK PROTECTION BITS
76543210
WPEN
0
1
X
BP1
BP0
WEL
RDY
STATUS REGISTER
Protected
Unprotected
Status
WPEN
WP
WEL
Blocks
Register
0
X
0
Protected
0
X
1
Protected
Writable
1
Low
0
Protected
1
Low
1
Protected
Writable
Protected
X
High
0
Protected
X
High
1
Protected
Writable
WRITE PROTECT ENABLE OPERATION
and the 25C01/02/04/08/16. Opcodes, byte addresses,
or data present on the SI pin are latched on the rising
edge of the SCK. Data on the SO pin is updated on the
falling edge of the SCK for SPI modes (0,0 & 1,1) .
CS
CS: Chip Select
CS is the Chip select pin. CS low enables the CAT25C01/
02/04/08/16 and
CS high disables the CAT25C01/02/
04/08/16.
CS high takes the SO output pin to high
impedance and forces the devices into a Standby Mode
(unless an internal write operation is underway)
The
CAT25C01/02/04/08/16 draws ZERO current in the
Standby mode. A high to low transition on
CS is required
prior to any sequence being initiated. A low to high
transition on
CS after a valid write sequence is what
initiates an internal write cycle.
BYTE ADDRESS
Device
Address Significant Bits
Address Don't Care Bits
# Address Clock Pulse
CAT25C01
A6 - A0
A7
8
CAT25C02
A7 - A0
8
CAT25C04
A7 - A0 (A8 = X bit from Opcode)
8
CAT25C08
A9 - A0
A15 - A10
16
CAT25C16
A10 - A0
A15 - A11
16
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