參數(shù)資料
型號: CAT511
英文描述: 8-Bit Digital POT with Independent Reference Inputs
中文描述: 8位數(shù)字電位器與獨立的基準(zhǔn)輸入
文件頁數(shù): 2/9頁
文件大?。?/td> 56K
代理商: CAT511
CAT511
2
Advanced Information
ABSOLUTE MAXIMUM RATINGS
Supply Voltage*
V
DD
to GND ......................................–0.5V to +7V
Inputs
CLK to GND............................–0.5V to V
DD
+0.5V
CS to GND..............................–0.5V to V
DD
+0.5V
DI to GND ...............................–0.5V to V
DD
+0.5V
RDY/BSY to GND...................–0.5V to V
DD
+0.5V
PROG to GND ........................–0.5V to V
DD
+0.5V
V
REF
H to GND ........................–0.5V to V
DD
+0.5V
V
REF
L to GND .........................–0.5V to V
DD
+0.5V
Outputs
D
0
to GND...............................–0.5V to V
DD
+0.5V
V
OUT
to GND...........................–0.5V to V
DD
+0.5V
Operating Ambient Temperature
Commercial (‘C’ suffix) .................... 0
°
C to +70
°
C
Industrial (‘I’ suffix)...................... – 40
°
C to +85
°
C
Junction Temperature ..................................... +150
°
C
Storage Temperature ....................... –65
°
C to +150
°
C
Lead Soldering (10 sec max) .......................... +300
°
C
* Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Absolute
Maximum Ratings are limited values applied individually while
other parameters are within specified operating conditions,
and functional operation at any of these conditions is NOT
implied. Device performance and reliability may be impaired by
exposure to absolute rating conditions for extended periods of
time.
DC ELECTRICAL CHARACTERISTICS:
V
DD
= +2.7V to +5.5V, V
REF
H = V
DD
, V
REF
L = 0V, unless otherwise specified
Symbol
Parameter
Conditions
RELIABILITY CHARACTERISTICS
Symbol
V
ZAP(1)
I
LTH(1)(2)
Parameter
Min
Max
Units
Test Method
ESD Susceptibility
Latch-Up
2000
100
Volts
mA
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Notes
:
1. This parameter is tested initially and after a design or process change that affects the parameter.
2. Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to V
CC
+ 1V.
Min
Typ
Max
Units
Resolution
8
Bits
Accuracy
INL
Integral Linearity Error
I
LOAD
= 250 nA, T
R
= C
T
R
= I
I
LOAD
= 1
μ
A, T
R
= C
T
R
= I
I
LOAD
= 250 nA, T
R
= C
T
R
= I
I
LOAD
= 1
μ
A, T
R
= C
T
R
= I
0.6
0.6
1.2
1.2
0.25
0.25
0.5
0.5
±
1
±
1
±
0.5
±
0.5
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
DNL
Differential Linearity Error
I
IH
I
IL
V
IH
V
IL
References
Input Leakage Current
Input Leakage Current
High Level Input Voltage
Low Level Input Voltage
V
IN
= V
DD
V
IN
= 0V
2
0
10
–10
V
DD
0.8
μ
A
μ
A
V
V
V
RH
V
RL
Z
IN
Logic Outputs
V
REF
H Input Voltage Range
V
REF
L Input Voltage Range
V
REF
H–V
REF
L Resistance
2.7
GND
28K
V
DD
V
V
V
DD
-2.7
V
OH
V
OL
High Level Output Voltage
Low Level Output Voltage
I
OH
= – 40
μ
A
I
OL
= 1 mA, V
DD
= +5V
I
OL
= 0.4 mA, V
DD
= +3V
V
DD
–0.3
0.4
0.4
V
V
V
Logic Inputs
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