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參數(shù)資料
| 型號(hào)： | CAT511 |
| 英文描述： | 8-Bit Digital POT with Independent Reference Inputs |
| 中文描述： | 8位數(shù)字電位器與獨(dú)立的基準(zhǔn)輸入 |
| 文件頁(yè)數(shù)： | 5/9頁(yè) |
| 文件大?。?/td> | 56K |
| 代理商： | CAT511 |
CAT511
5
Advanced Information
PIN DESCRIPTION
Pin
Name
Function
1
2
3
4
5
6
7
V
DD
CLK
RDY/
BSY
CS
DI
DO
PROG
Power supply positive
Clock input pin
Ready/Busy output
Chip select
Serial data input pin
Serial data output pin
EEPROM Programming Enable
Input
Power supply ground
Minimum DAC 1 output voltage
No Connect
No Connect
DAC 1 output
No Connect
Maximum DAC 1 output voltage
8
9
GND
V
REF
L1
NC
NC
V
OUT
1
NC
V
REF
H1
10
11
12
13
14
DEVICE OPERATION
The CAT511 is an 8-bit Digital to Analog Converter
(DAC) whose output can be programmed to any one of
256 individual voltage steps. Once programmed, the
output setting is retained in non-volatile EEPROM
memory and will not be lost when power is removed from
the chip. Upon power up the DACs return to the setting
stored in EEPROM memory. The DAC can be written to
and read from without effecting the output voltage during
the read or write cycle. The output can also be adjusted
without altering the stored output setting, which is useful
for testing a new output setting before storing in memory.
DIGITAL INTERFACE
The CAT511 employs a standard 3 wire serial control
interface consisting of Clock (CLK), Chip Select (CS)
and Data In (DI) inputs. For all operations, address and
data are shifted in LSB first. In addition, all digital data
must be preceded by a logic “1” as a start bit. The DAC
address and data are clocked into the DI pin on the
clock’s rising edge. When sending multiple blocks of
information a minimum of two clock cycles is required
between the last block sent and the next start bit.
Multiple devices may share a common input data line by
selectively activating the CS control of the desired IC.
Data Outputs (DO) can also share a common line
because the DO pin is Tri-Stated and returns to a high
impedance when not in use.
CHIP SELECT
Chip Select (CS) enables and disables the CAT511’s
read and write operations. When CS is high data may be
read to or from the chip, and the Data Output (DO) pin is
active. Data loaded into the DAC control register will
remain in effect until CS goes low. Bringing CS to a logic
low returns all DAC outputs to the settings stored in
EEPROM memory and switches DO to its high imped-
ance Tri-State mode.
Because CS functions like a reset the CS pin has been
desensitized with a 30 ns to 90 ns filter circuit to prevent
noise spikes from causing unwanted resets and the loss
of volatile data.
CLOCK
The CAT511’s clock controls both data flow in and out of
the device and EEPROM memory cell programming.
Serial data is shifted into the DI pin and out of the DO pin
on the clock’s rising edge. While it is not necessary for
the clock to be running between data transfers, the clock
must be operating in order to write to EEPROM memory,
even though the data being saved may already be
resident in the DAC control register.
No clock is necessary upon system power-up. The
CAT511’s internal power-on reset circuitry loads data
from EEPROM to the DAC without using the external
clock.
DAC addressing is as follows:
DAC OUTPUT
A0
A1
V
OUT
1
0
1
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