參數(shù)資料
型號: CAT515
英文描述: 8-Bit Quad Digital POT with Independent Reference Inputs(帶獨立電壓基準輸入的四路,8位數(shù)字電位器)
中文描述: 8位四路數(shù)字電位器與獨立的基準輸入(帶獨立電壓基準輸入的四路,8位數(shù)字電位器)
文件頁數(shù): 3/12頁
文件大小: 85K
代理商: CAT515
CAT515
3
Doc. No. 25077-00 2/98 M-1
DC ELECTRICAL CHARACTERISTICS
(Cont.)
:
V
DD
= +2.7V to +5.5V, V
REF
H = V
DD
, V
REF
L = 0V
, unless otherwise specified
Symbol
Analog Output
FSO
ZSO
I
L
R
OUT
Parameter
Conditions
Min
Typ
Max
Units
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Digital
t
CSMIN
t
CSS
t
CSH
t
DIS
t
DIH
t
DO1
t
DO0
t
HZ
t
LZ
t
BUSY
t
PS
t
PROG
t
CLK
H
t
CLK
L
f
C
Analog
t
DS
Minimum CS Low Time
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
Output Delay to 1
Output Delay to 0
Output Delay to High-Z
Output Delay to Low-Z
Erase/Write Cycle Time
PROG Setup Time
Minimum Pulse Width
Minimum CLK High Time
Minimum CLK Low Time
Clock Frequency
150
100
0
50
50
150
700
500
300
DC
400
400
4
150
150
5
1
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
MHz
DAC Settling Time to 1 LSB
C
LOAD
= 10 pF, V
DD
= +5V
C
LOAD
= 10 pF, V
DD
= +3V
3
6
10
10
μ
s
μ
s
Pin Capacitance
C
IN
C
OUT
Input Capacitance
Output Capacitance
V
IN
= 0V, f = 1 MHz
(2)
V
OUT
= 0V, f = 1 MHz
2)
8
6
pF
pFNotes
C
L
= 100 pF,
see note 1
AC ELECTRICAL CHARACTERISTICS:
V
DD
= +2.7V to +5.5V, V
REF
H = V
DD
, V
REF
L = 0V
, unless otherwise specified
Full-Scale Output Voltage
Zero-Scale Output Voltage
DAC Output Load Current
DAC Output Impedance
V
R
= V
REF
H – V
REF
L
V
R
= V
REF
H – V
REF
L
0.99 V
R
0.995 V
R
0.005 V
R
V
V
μ
A
0.01 V
R
1
100K
150K
1
V
DD
= V
REF
H = +5V
V
DD
= V
REF
H = +3V
I
LOAD
= 1
μ
A
PSSR
Temperature
TC
O
Power Supply Rejection
LSB / V
V
OUT
Temperature Coefficient
V
DD
= +5V, I
LOAD
= 250nA
V
REF
H= +5V, V
REF
L = 0V
V
REF
H to V
REF
L
200
μ
V/
°
C
TC
REF
Temperature Coefficient of
V
REF
Resistance
700
ppm /
°
C
Power Supply
I
DD1
I
DD2
Supply Current (Read)
Supply Current (Write)
Normal Operating
V
DD
= 5V
V
DD
= 3V
2.7
40
1200
600
50
2000
1200
5.5
μ
A
μ
A
μ
A
V
V
DD
Operating Voltage Range
Notes: 1. All timing measurements are defined at the point of signal crossing V
DD
/ 2.
2. These parameters are periodically sampled and are not 100% tested.
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