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參數(shù)資料
| 型號： | CAT515 |
| 英文描述： | 8-Bit Quad Digital POT with Independent Reference Inputs(帶獨立電壓基準輸入的四路，8位數(shù)字電位器) |
| 中文描述： | 8位四路數(shù)字電位器與獨立的基準輸入（帶獨立電壓基準輸入的四路，8位數(shù)字電位器） |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 85K |
| 代理商： | CAT515 |
CAT515
6
Doc. No. 25077-00 2/98 M-1
As data transfers are edge triggered clean clock transi-
tions are necessary to avoid falsely clocking data into the
control registers. Standard CMOS and TTL logic fami-
lies work well in this regard and it is recommended that
any mechanical switches used for breadboarding or
device evaluation purposes be debounced by a flip-flop
or other suitable debouncing circuit.
V
REF
V
REF
, the voltage applied between pins V
REF
H
&V
REF
L,
sets the DAC’s Zero to Full Scale output range where
V
REF
L = Zero and V
REF
H
= Full Scale. V
REF
can span the
full power supply range or just a fraction of it. In typical
applications V
REF
H
&V
REF
L are connected across the
power supply rails. When using less than the full supply
voltage be mindfull of the limits placed on V
REF
H and
V
REF
L as specified in the "References" section of DC
"Electrical Characteristics".
READY/
BUSY
When saving data to non-volatile EEPROM memory, the
Ready/Busy ouput (RDY/
BSY
) signals the start and
duration of the EEPROM erase/write cycle. Upon receiv-
ing a command to store data (PROG goes high) RDY/
BSY
goes low and remains low until the programming
cycle is complete. During this time the CAT515 will
ignore any data appearing at DI and no data will be
output on DO.
RDY/
BSY
is internally ANDed with a low voltage detec-
tor circuit monitoring V
DD.
If V
DD
is below the minimum
value required for EEPROM programming, RDY/
BSY
will remain high following the program command indicat-
ing a failure to record the desired data in non-volatile
memory.
DATA OUTPUT
Data is output serially by the CAT515, LSB first, via the
Data Out (DO) pin following the reception of a start bit
and two address bits by the Data Input (DI). DO
becomes active whenever CS goes high and resumes
its high impedance Tri-State mode when CS returns low.
Tri-Stating the DO pin allows several 515s to share a
single serial data line and simplifies interfacing multiple
515s to a microprocessor.
WRITING TO MEMORY
Programming the CAT515’s EEPROM memory is ac-
complished through the control signals: Chip Select
(CS) and Program (PROG). With CS high, a start bit
followed by a two bit DAC address and eight data bits are
clocked into the DAC control register via the DI pin. Data
enters on the clock’s rising edge. The DAC output
changes to its new setting on the clock cycle following
D7, the last data bit.
Programming is accomplished by bringing PROG high
sometime after the start bit and at least 150 ns prior to the
rising edge of the clock cycle immediately following the
D7 bit. Two clock cycles after the D7 bit the DAC control
register will be ready to receive the next set of address
and data bits. The clock must be kept running through-
out the programming cycle. Internal control circuitry
takes care of generating and ramping up the program-
ming voltage for data transfer to the EEPROM cells. The
CAT515’s EEPROM memory cells will endure over
100,000 write cycles and will retain data for a minimum
of 20 years without being refreshed.
READING DATA
Each time data is transferred into a DAC control register
currently held data is shifted out via the D0 pin, thus in
every data transaction a read cycle occurs. Note,
however, that the reading process is destructive. Data
must be removed from the register in order to be read.
Figure 2 depicts a Read Only cycle in which no change
occurs in the DAC’s output. This feature allows
μ
Ps to
poll DACs for their current setting without disturbing the
output voltage but it assumes that the setting being read
is also stored in EEPROM so that it can be restored at the
end of the read cycle. In Figure 2 CS returns low before
the 13
th
clock cycle completes. In doing so the EEPROM’s
Figure 1. Writing to Memory
Figure 2. Reading from Memory
A0
A1
1
DO
DI
CS
PROG
DAC
OUTPUT
to
CURRENT
NON-VOLATILE
D0
D1
D2
D3
D4
D5
D6
D7
CURRENT DAC DATA
RDY/BSY
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
D0
D1
D2
D3
D4
D5
D6
D7
1
NEW DAC DATA
CURRENT DAC DATA
CURRENT
NON-VOLATILE
DAC
OUTPUT
PROG
DO
DI
CS
DANEW
VOLATILE
DANEW
NON-VOLATILE
to
RDY/BSY
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