V
參數(shù)資料
型號: CAT5172TBI-50GT3
廠商: ON Semiconductor
文件頁數(shù): 3/10頁
文件大?。?/td> 0K
描述: IC POT DGTL 50K 256TAP SOT23-8
標(biāo)準包裝: 3,000
接片: 256
電阻(歐姆): 50k
電路數(shù): 1
溫度系數(shù): 標(biāo)準值 100 ppm/°C
存儲器類型: 易失
接口: I²C(芯片選擇)
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: SOT-23-8
供應(yīng)商設(shè)備封裝: SOT-23-8
包裝: 帶卷 (TR)
CAT5172
http://onsemi.com
2
SPI
INTERFACE
WIPER
REGISTER
CLK
A
B
W
SDI
GND
Figure 1. Functional Block Diagram
VDD
CS
Table 1. ORDERING INFORMATION
Part Number
Resistance
Temperature Range
Package
Shipping
CAT5172TBI50GT3
50 kW
40C to 85C
SOT238
(PbFree)
3000/Tape & Reel
CAT5172TBI00GT3
100 kW
3000/Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
1. For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Device
Nomenclature document, TND310/D, available at www.onsemi.com.
Table 2. PIN FUNCTION DESCRIPTION
Pin No.
Pin Name
Description
1
W
Resistor’s Wiper Terminal.
2
VDD
Positive Power Supply.
3
GND
Digital Ground.
4
CLK
Serial Clock Input. Positive edge triggered.
5
SDI
Serial Data Input.
6
CS
Chip Select Input, Active Low. When CS returns high, data will be loaded into the DAC register.
7
B
Bottom Terminal of resistive element.
8
A
Top Terminal of resistive element.
Table 3. ABSOLUTE MAXIMUM RATINGS (Note 2)
Rating
Value
Unit
VDD to GND
0.3 to 6.5
V
VA, VB, VW to GND
VDD
IMAX
20
mA
Digital Inputs and Output Voltage to GND
0 to 6.5
V
Operating Temperature Range
40 to +85
C
Maximum Junction Temperature (TJMAX)
150
C
Storage Temperature
65 to +150
C
Lead Temperature (Soldering, 10 sec)
300
C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and
maximum applied voltage across any two of the A, B, and W terminals at a given resistance.
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