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參數(shù)資料
| 型號(hào)： | CAT5172TBI-50GT3 |
| 廠商： | ON Semiconductor |
| 文件頁(yè)數(shù)： | 5/10頁(yè) |
| 文件大小： | 0K |
| 描述： | IC POT DGTL 50K 256TAP SOT23-8 |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 接片： | 256 |
| 電阻（歐姆）： | 50k |
| 電路數(shù)： | 1 |
| 溫度系數(shù)： | 標(biāo)準(zhǔn)值 100 ppm/°C |
| 存儲(chǔ)器類型： | 易失 |
| 接口： | I²C（芯片選擇） |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-8 |
| 供應(yīng)商設(shè)備封裝： | SOT-23-8 |
| 包裝： | 帶卷 (TR) |
CAT5172
http://onsemi.com
4
Table 4. ELECTRICAL CHARACTERISTICS: 50 kW and 100 kW Versions (continued)
VDD = 5 V 10%, or 3 V 10%; VA = VDD; VB = 0 V; –40C < TA < +85C; unless otherwise noted.
Parameter
Unit
Max
Typ
(Note 3)
Min
Symbol
Test Conditions
Bandwidth –3 dB
RAB = 50 kW / 100 kW, Code = 0x80
BW
100/40
kHz
Total Harmonic Distortion
VA =1 V rms, VB = 0 V,
f = 1 kHz, RAB = 10 kW
THDW
0.05
%
VW Settling Time (50 kW/100 kW)
VA = 5 V, VB = 0 V, 1 LSB error band
tS
2
ms
3. Typical specifications represent average readings at +25C and VDD = 5 V.
4. Resistor position nonlinearity error RINL is the deviation from an ideal value measured between the maximum resistance and the
minimum resistance wiper positions. RDNL measures the relative step change from ideal between successive tap positions. Parts are
guaranteed monotonic.
5. VAB = VDD, Wiper (VW) = no connect.
6. INL and DNL are measured at VW with the digital POT configured as a potentiometer divider similar to a voltage output D/A converter.
VA = VDD and VB = 0 V. DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions.
7. Resistor terminals A, B, W have no limitations on polarity with respect to each other.
8. Guaranteed by design and not subject to production test.
9. PDISS is calculated from (IDD x VDD). CMOS logic level inputs result in minimum power dissipation.
10.All dynamic characteristics use VDD = 5 V.
Table 5. TIMING CHARACTERISTICS: 50 kW and 100 kW Versions
VDD = 5 V 10%, or 3 V 10%; VA = VDD; VB = 0 V; –40C < TA < +85C; unless otherwise noted.
Parameter
Test Conditions
Symbol
Min
Typ
(Note 11)
Max
Unit
Clock Frequency
fCLK
25
MHz
Input Clock Pulse width
Clock level high or low
tCH, tCL
20
ns
Data Setup Time
tDS
5
ns
Data Hold Time
tDH
5
ns
CS Setup Time
TCSS
15
ns
CS High Pulse Width
TCSW
40
ns
CLK Fall to CS Fall Hold Time
TCSH0
0
ns
CLK Fall to CS Rise Hold Time
TCSH1
0
ns
CS Rise to Clock Rise Setup
TCS1
10
ns
11. Typical specifications represent average readings at +25C and VDD = 5 V.
12.Guaranteed by design and not subject to production test.
13.See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed
from a voltage level of 1.5 V.
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