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參數(shù)資料
| 型號： | CB-C8VM |
| 廠商： | NEC Corp. |
| 英文描述： | Cell-Based CMOS ASIC(CMOS 特殊集成電路) |
| 中文描述： | 細胞的CMOS集成電路的CMOS（特殊集成電路） |
| 文件頁數(shù)： | 5/8頁 |
| 文件大小： | 41K |
| 代理商： | CB-C8VM |
5
CB-C8VX/VM
Input/Output Capacitance
(V
DD
=V
I
= 0 V; f=1 MHz)
Terminal
Symbol
Typ
Max
Unit
Input
C
IN
10
20
pF
Output
C
OUT
10
20
pF
I/O
C
I/O
10
20
pF
(1)
Values include package pin capacitance
Absolute Maximum Ratings
Power supply voltage, V
DD
3.3 V supply
–0.5 to +4.6 V
5 V supply
–0.5 to +6.0 V
I/O voltage, V
I
/V
O
3.3 V interface block
–0.5 to +4.6 V and (V
I
/V
O
< V
DD
+0.5 V)
5 V-tolerant block
–0.5 to +6.6 V and (V
I
/V
O
< V
DD
+3.0 V)
5 V swing block
–0.5 to +6.0 V and (V
I
/V
O
< V
DD
+0.5 V)
Latch-up current, I
LATCH
>1 A (typ)
Operating temperature, T
OPT
–40 to +85°C
Storage temperature, T
STG
–65 to +150°C
AC Characteristics
(V
DD
= 3.3 V ± 0.3 V; T
J
= –40 to +125°C)
Parameter
Toggle frequency
Delay time
2-input NAND (F322)
Symbol
f
TOG
Min
Typ
480
Max
Unit
MHz
Conditions
D-F/F; F/O = 2 mm
t
PD
t
PD
t
PD
t
PD
t
SETUP
t
HOLD
t
PD
t
PD
t
PD
t
PD
t
PD
t
R
t
F
236
272
ps
ps
F/O = 1; L = 0 mm
F/O = 2; L = typ
Flip-flop (F661)
777
865
420
580
126
228
1.24
ps
ps
ps
ps
ps
ps
ns
F/O = 1; L = 0 mm
F/O = 2; L = typ
—
—
F/O = 1; L = 0 mm
F/O = 2; L = typ
C
L
= 15 pF
C
L
= 15 pF
C
L
= 15 pF
C
L
= 15 pF
C
L
= 15 pF
Input buffer (FI01)
Output buffer (9 mA) 3.3 V
Output buffer (9 mA) 5 V-tolerant
Output buffer (6 mA) 5 V-swing
Output rise time (9 mA)
Output fall time (9 mA)
4.262
2.698
1.88
1.32
ns
ns
ns
ns
Recommended Operating Conditions
(V
DD
= 3.3 V ± 0.165 V; V
CC
= 5.0 V ± 0.5 V; T
J
= –40 to +125°C)
3.3 V Interface
Block
5 V Tolerant
Block
(CB-C8VX/VM)
Min
5 V Swing
CMOS Level
(CB-C8VM)
Min
5 V Swing
TTL Level
(CB-C8 VM)
Min
Parameter
Symbol
Min
Max
Max
Max
Max
Unit
I/O power supply voltage
V
DD
3.0
3.6
3.0
3.6
4.5
5.5
4.75
5.25
V
Junction temperature
T
J
–40
+125
–40
+125
–40
+125
–40
+125
°C
High-level input voltage
V
IH
2.0
V
DD
2.0
5.5
0.7 V
DD
V
DD
2.0
V
DD
V
Low-level input voltage
V
IL
0
0.8
0
0.8
0
0.3 V
DD
0
0.8
V
Positive trigger voltage
V
P
1.2
2.4
1.2
2.4
1.8
4.0
1.2
2.4
V
Negative trigger voltage
V
N
0.6
1.8
0.6
1.8
0.6
3.1
0.6
1.8
V
Hysteresis voltage
V
H
0.3
1.5
0.3
1.5
0.3
1.5
0.3
1.5
V
Input rise/fall time
t
R
, t
F
0
200
0
200
0
200
0
200
ns
Input rise/fall time, Schmitt
t
R
, t
F
0
10
0
10
0
10
0
10
ms
Power Consumption
Description
Internal gate
(1)
Limits
Unit
1.04
μW/MHz
Input block
—
μW/MHz
Output block
—
μW/MHz
(1)
Assumes 30% internal gate switching at one time
Caution:
Exposure to absolute maximum ratings for extended periods may affect
device reliability; exceeding the ratings could cause permanent damage. The device
should not be operated outside the recommended operating conditions.
Caution:
Exposure to absolute maximum ratings for extended periods may affect
device reliability; exceeding the ratings could cause permanent damage. The device
should not be operated outside the recommended operating conditions.
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