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參數(shù)資料
| 型號： | CB-C8VX |
| 廠商： | NEC Corp. |
| 英文描述： | Cell-Based CMOS ASIC(CMOS 特殊集成電路) |
| 中文描述： | 細(xì)胞的CMOS集成電路的CMOS（特殊集成電路） |
| 文件頁數(shù)： | 2/8頁 |
| 文件大小： | 41K |
| 代理商： | CB-C8VX |
CB-C8VX/VM
2
5-Volt-Tolerant Interface
CB-C8VX supports both 3.3-volt and 5-volt-tolerant
signaling. The 5-volt-tolerant buffers enable CB-C8VX
devices to communicate with 5-volt TTL signals while
protecting the ASIC. CB-C8VX requires only a 3.3-volt
power supply.
Integration and Performance
Gate complexities up to 703K usable gates can be
integrated on the largest of 36 die sizes, each routable
with 2- or 3-metal layers. This gives enough flexibility
to optimally fit design needs. Twenty-two die sizes
offer a single I/O pad ring and 14 are equipped with a
staggered dual pad ring in order to achieve a high pad-
to-gate ratio. For details, please refer to Table 2 and
Table 3.
The family offers an extensive library of primitive
macrofunctions characterized for 3.3-volt operation.
Each of these blocks has several different drive
strengths, allowing the synthesis tool to select the most
suitable block for the required internal load. This
generally reduces the design overhead without
influencing design performance. The internal gate
delay for a two-input NAND gate is 110 picoseconds
(ps), (F/O=1, L=0mm) and 220 ps under loaded
conditions (F/O=2, L=2mm).
To meet today's high-speed demands, high-perform-
ance I/O macros are mandatory. CB-C8VX/VM
supports macros such as GTL and HSTL for fast, low-
power data transfer, PLLs to synchronize on-chip
system clocks, and PCI signaling standards. Also,
CB-C8VX/VM offers a variety of macrofunctions to be
incorporated on a single chip. These macrofunctions
include CPU cores, peripheral devices, RAM/ROM and
analog functions, enabling designers to create systems
on silicon.
Low Power Consumption
NEC's CB-C8VX/VM Ti-Silicide process features
exceptionally low power dissipation to facilitate high-
speed operation without the need of costly package
options, and drastically increases battery life for hand-
held applications. At 3.3-volts, power dissipation for
internal cells is 1.04 μW/gate/MHz.
Table 2. CB-C8VX/VM Die Steps
(124μ pad pitch)
Step
I/O
Max. Usable Gates
(1)
2 Layer
3 Layer
B18
88
13078
19617
B57
104
18797
28195
B97
120
25438
38156
C37
136
33219
49828
C76
152
42016
63023
D16
168
51703
77555
D55
184
62547
93820
D75
192
67969
101953
E15
208
80484
120727
E54
224
93875
140813
E94
240
106000
159000
F34
256
120969
181453
F74
272
136641
204961
G14
288
153500
230250
G53
304
171234
256852
G93
320
183078
274617
H33
336
202328
303492
H72
352
222219
333328
J32
376
254094
381141
J71
392
275813
413719
K11
408
298797
448195
K90
440
347031
520547
Single pad ring die steps.
(1) Glue logic only, with average utilization.
Table 3. CB-C8VX/VM Die Steps
(80μ staggered pad pitch)
Step
I/O
Max. Usable Gates
(1)
2 Layer
3 Layer
B73T
148
18844
28266
C37T
188
30250
45375
C50T
196
32703
49055
D01T
228
44000
66000
D52T
260
57047
85570
D90T
284
67797
101695
E54T
324
88281
132422
F18T
364
109125
163688
F70T
396
128875
193313
G34T
436
155297
232945
H49T
508
202766
304148
J51T
572
256047
384070
K92T
660
337531
506297
M97T
788
468984
703477
Dual pad ring die steps.
(1) Glue logic only, with average utilization.
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