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參數資料
| 型號： | CBTL12131ET |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 模擬信號調理 |
| 英文描述： | DisplayPort multiplexer for bidirectional video in all-in-one computer systems |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PBGA64 |
| 封裝： | 6 X 6 MM, 0.80 MM HEIGHT, 0.50 MM PITCH, PLASTIC, MO-195, SOT543-1, TFBGA-64 |
| 文件頁數： | 12/28頁 |
| 文件大?。?/td> | 215K |
| 代理商： | CBTL12131ET |
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CBTL12131
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 25 February 2011
2 of 28
NXP Semiconductors
CBTL12131
DisplayPort multiplexer for bidirectional video
TFBGA64 package with 0.5 mm ball pitch; owing to its high level of integration and
versatility, it is eminently suitable for use in computers employing bidirectional DisplayPort
video.
2.
Features and benefits
2.1 High-speed DisplayPort Main Link multiplexing
Switch path topologies supporting:
‘dual through’ mode (two GPUs to two displays simultaneously)
‘external source’ mode (external source to internal display)
Supports DisplayPort v1.1a at 2.7 Gbit/s
High-bandwidth analog pass-gate technology
Configurable equalization in ‘external source’ mode path
Pre-emphasis level control for equalizer in ‘external source’ mode path
Very low intra-pair differential skew of < 5 ps
Very low inter-pair skew of < 180 ps
2.2 DDC and AUX multiplexing
Switch path topologies supporting:
‘dual through’ mode (two GPUs to two displays)
‘external source’ mode (external source to internal display)
‘AC coupling bypass’ mode on Port A (for external ++DP sink)
Supports DisplayPort v1.1a AUX channel
Supports DDC/I2C-bus multiplexing
High-bandwidth analog pass-gate technology
2.3 HPD channel management
Active logic management of HPD signals
Bidirectional HPD I/O for external connector (Port B)
HPD input for integrated DisplayPort display (Port D)
Two HPD outputs to both GPUs, one for internal (Port C) and one for external video
(Port A)
5 V tolerance on all HPD inputs
3.3 V LVTTL logic output levels for all HPD outputs
Internal 200 k
Ω pull-down resistor on Port B and Port D HPD input ensures default
LOW when no sink is connected
2.4 Link state detection, configuration and reporting
Detection of DC state of AUX_P and AUX_N lines of external display (Port B)
Filtering of HPD interrupt pulse from external display (Port B)
Reporting of detected/filtered Port B AUX and HPD states via CMOS outputs (to
external system controller)
AUX channel bias control inputs for Port B to allow configuration as source or sink
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相關代理商/技術參數 |
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| CBTL12131ET,518 | 功能描述:編碼器、解碼器、復用器和解復用器 1.1 MUX BI-DRC VIDEO 1 DISPLAYPORT CONN RoHS:否 制造商:Micrel 產品:Multiplexers 邏輯系列:CMOS 位數: 線路數量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| CBTL12131ET518 | 制造商:NXP 功能描述: 制造商:NXP Semiconductors 功能描述: |
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| CBTL1610A1UKAZ | 制造商:NXP Semiconductors 功能描述:LINEAR IC |
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