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參數(shù)資料
| 型號： | CD4047BDMS |
| 廠商： | INTERSIL CORP |
| 元件分類： | 諧振器 |
| 英文描述： | 4000/14000/40000 SERIES, MONOSTABLE MULTIVIBRATOR, CDIP14 |
| 封裝： | DIP-14 |
| 文件頁數(shù)： | 1/15頁 |
| 文件大?。?/td> | 127K |
| 代理商： | CD4047BDMS |
7-897
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
CD4047BMS
CMOS Low-Power
Monostable/Astable Multivibrator
Description
CD4047BMS consists of a gatable astable multivibrator with logic tech-
niques incorporated to permit positive or negative edge triggered
monostable multivibrator action with retriggering and external counting
options.
Inputs include +TRIGGER, -TRIGGER, ASTABLE, ASTABLE,
RETRIGGER, and EXTERNAL RESET. Buffered outputs are Q, Q, and
OSCILLATOR. In all modes of operation, an external capacitor must be
connected between C-Timing and RC-Common terminals, and an
external resistor must be connected between the R-Timing and RC-
Common terminals.
Astable operation is enabled by a high level on the ASTABLE input or a
low level on the ASTABLE input, or both. The period of the square wave
at the Q and Q Outputs in this mode of operation is a function of the
external components employed. “True” input pulses on the ASTABLE
input or “Complement” pulses on the ASTABLE input allow the circuit to
be used as a gatable multivibrator. The OSCILLATOR output period will
be half of the Q terminal output in the astable mode. However, a 50%
duty cycle is not guaranteed at this output.
The CD4047BMS triggers in the monostable mode when a positive
going edge occurs on the +TRIGGER input while the -TRIGGER is held
low. Input pulses may be of any duration relative to the output pulse.
If retrigger capability is desired, the RETRIGGER input is pulsed. The
retriggerable mode of operation is limited to positive going edge. The
CD4047BMS will retrigger as long as the RETRIGGER input is high,
with or without transitions (See Figure 31)
An external countdown option can be implemented by coupling “Q” to
an external “N” counter and resetting the counter with trigger pulse. The
counter output pulse is fed back to the ASTABLE input and has a dura-
tion equal to N times the period of the multivibrator.
A high level on the EXTERNAL RESET input assures no output pulse
during an “ON” power condition. This input can also be activated to ter-
minate the output pulse at any time. For monostable operation, when-
ever VDD is applied, an internal power on reset circuit will clock the Q
output low within one output period (tM).
The CD4047BMS is supplied in these 14-lead outline packages:
Pinout
CD4047BMS
TOP VIEW
Braze Seal DIP
H4Q
Frit Seal DIP
H1B
Ceramic Flatpack
H3W
C
R
R-C COMMON
ASTABLE
-TRIGGER
VSS
VDD
OSC OUT
RETRIGGER
Q
EXT. RESET
+TRIGGER
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Features
High Voltage Type (20V Rating)
Low Power Consumption: Special CMOS Oscillator
Conguration
Monostable (One-Shot) or Astable (Free-Running)
Operation
True and Complemented Buffered Outputs
Only One External R and C Required
Buffered Inputs
100% Tested for Quiescent Current at 20V
Standardized, Symmetrical Output Characteristics
5V, 10V and 15V Parametric Ratings
Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specications for Description of
‘B’ Series CMOS Devices”
Monostable Multivibrator Features
Positive or Negative Edge Trigger
Output Pulse Width Independent of Trigger Pulse
Duration
Retriggerable Option for Pulse Width Expansion
Internal Power-On Reset Circuit
Long Pulse Widths Possible Using Small RC Compo-
nents by Means of External Counter Provision
Fast Recovery Time Essentially Independent of Pulse
Width
Pulse-Width Accuracy Maintained at Duty Cycles
Approaching 100%
Astable Multivibrator Features
Free-Running or Gatable Operating Modes
50% Duty Cycle
Oscillator Output Available
Good Astable Frequency Stability: Frequency Deviation:
-=
±2% + 0.03%/oC at 100kHz
-=
±0.5% + 0.015%/oC at 10kHz (Circuits “Trimmed”
to Frequency VDD = 10V
± 10%
Applications
Digital equipment where low power dissipation and/or high noise
immunity are primary design requirements
Envelope Detection
Frequency Multiplication
Frequency Division
Frequency Discriminators
Timing Circuits
Time Delay Applications
December 1992
File Number
3313
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