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參數(shù)資料
| 型號： | CD4047BDMS |
| 廠商： | INTERSIL CORP |
| 元件分類： | 諧振器 |
| 英文描述： | 4000/14000/40000 SERIES, MONOSTABLE MULTIVIBRATOR, CDIP14 |
| 封裝： | DIP-14 |
| 文件頁數(shù)： | 6/15頁 |
| 文件大?。?/td> | 127K |
| 代理商： | CD4047BDMS |
7-910
CD4047BMS
Retrigger Mode Operation
The CD4047BMS can be used in the retrigger mode to extend
the output pulse duration, or to compare the frequency of an
input signal with that of the internal oscillator. In the retrigger
mode the input pulse is applied to terminal 12, and the output is
taken from terminal 10 or 11. As shown in Figure 31 normal
monostable action is obtained when one retrigger pulse is
applied. Extended pulse duration is obtained when more than
one pulse is applied.
For two input pulses, tRE = t1 + t1 + 2t2. For more than two
pulses, the output pulse width is an integral number of time peri-
ods, with the rst time period being t1 + t2, typically, 2.48RC, and
all subsequent time periods being t1 + t2, typically, 2.2RC.
External Counter Option
Time tM can be extended by any amount with the use of external
counting circuitry. Advantages include digitally controlled pulse
duration, small timing capacitors for long time periods, and
extremely fast recovery time. A typical implementation is shown
in Figure 32. The pulse duration at the output is
text = (N - 1) (tA) + (tM + tA/2)
where text = pulse duration of the circuitry, and N is the number
of counts used.
FIGURE 32. IMPLEMENTATION OF EXTERNAL COUNTER OPTION
Timing Component Limitations
The capacitor used in the circuit should be non polarized and
have low leakage (i.e. the parallel resistance of the capacitor
should be at least an order of magnitude greater than the exter-
nal resistor used). There is no upper or lower limit for either R or
C value to maintain oscillation.
AST
Q
CD4047BMS
CD4017BMS
R
CL
OUT
11
12
INPUT
PULSE
OPTIONAL
BUFFER
TEXT
However, in consideration of accuracy, C must be much larger
than the inherent stray capacitance in the system (unless this
capacitance can be measured and taken into account). R must
be much larger than the CMOS “ON” resistance in series with
it, which typically is hundreds of
. In addition, with very large
values of R, some short term instability with respect to time may
be noted.
The recommended values for these components to maintain
agreement with previously calculated formulas without trimming
should be:
C
≥ 100pF, up to any practical value, for astable modes;
C
≥ 1000pF, up to any practical value for monostable modes.
10k
≤ R ≤ 1M
Power Consumption
In the standby mode (Monostable or Astable), power dissipa-
tion will be a function of leakage current in the circuit, as shown
in the static electrical characteristics. For dynamic operation,
the power needed to charge the external timing capacitor C is
given by the following formula:
Astable Mode:
P = 2CV2f. (Output at terminal No. 13)
P = 4CV2f. (Output at terminal Nos. 10 and 11)
Monostable Mode:
(Output at terminal Nos. 10 to 11)
The circuit is designed so that most of the total power is con-
sumed in the external components. In practice, the lower the
values of frequency and voltage used, the closer the actual
power dissipation will be to the calculated value.
Because the power dissipation does not depend on R, a
design for minimum power dissipation would be a small value
of C. The value of R would depend on the desired period
(within the limitations discussed above). See Figures 26, 27,
and 28 for typical power consumption in astable mode.
P =
(2.9CV2) (Duty Cycle)
T
FIGURE 31. RETRIGGER MODE WAVEFORMS
t1
t2
tRE
+TRIGGER &
t1
t2
t1
t2
tRE
t1
t2
t1
t2
t1
t2
t1
t2
tRE
t1
t2
t1
t2
t1
t2
tRE
RETRIGGER
TERMINALS
8 & 12
OSC OUTPUT
TERMINAL 13
Q OUTPUT
TERMINAL 10
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