參數(shù)資料
型號： CD74HCT7046AM
廠商： TEXAS INSTRUMENTS INC
元件分類： XO, clock
英文描述： PHASE LOCKED LOOP, PDSO16
封裝： GREEN, PLASTIC, SOIC-16
文件頁數(shù)： 14/29頁
文件大?。?/td> 485K
代理商： CD74HCT7046AM
21
Lock Detector Circuit
The lock detector feature is very useful in data synchroniza-
tion, motor speed control, and demodulation. By adjusting
the value of the lock detector capacitor so that the lock out-
put will change slightly before actually losing lock, the
designer can create an “early warning” indication allowing
corrective measures to be implemented. The reverse is also
true, especially with motor speed controls, generators, and
clutches that must be set up before actual lock occurs or dis-
connected during loss of lock.
When using phase comparator 1, the detector will only indi-
cate a lock condition on the fundamental frequency and not
on the harmonics, which PC1 will lock on.
PLL Conditions with
No Signal at the
SIGIN Input
PC1
VCO adjusts to fo with φDEMOUT = 90
o and V
VCOIN = 1/2 VCC (see Figure 2)
PC2
VCO adjusts to fMIN with φDEMOUT = -360
o and V
VCOIN = 0V (see Figure 4)
PLL Frequency
Capture Range
PC1 or PC2
Loop Filter Component Selection
PLL Locks on
Harmonics at Center
Frequency
PC1
Yes
PC2
No
Noise Rejection at
Signal Input
PC1
High
PC2
Low
AC Ripple Content
when PLL is Locked
PC1
fr = 2fi, large ripple content at φDEMOUT = 90
o
PC2
fr = fi, small ripple content at φDEMOUT = 0
o
SUBJECT
PHASE
COMPARATOR
DESIGN CONSIDERATIONS
A small capture range (2fc) is obtained if τ > 2fc ≈ (1/π) (2πfL/τ1.)
1/2
FIGURE 48. SIMPLE LOOP FILTER FOR PLL WITHOUT OFFSET
(A)
τ1 = R3 x C2
(B) AMPLITUDE CHARACTERISTIC
(C) POLE-ZERO DIAGRAM
R3
C2
INPUT
OUTPUT
|F(j
ω)|
ω
-1/
τ
FIGURE 49. SIMPLE LOOP FILTER FOR PLL WITH OFFSET
(A)
τ2 = R4 x C2;
(B) AMPLITUDE CHARACTERISTIC
(C) POLE-ZERO DIAGRAM
|F(j
ω)|
ω
-1/
τ2
R3
C2
INPUT
OUTPUT
τ3 = (R3 + R4) x C2
-1/
τ3
m
1/
τ3 1/τ2
R4
m =
R4
R3 + R4
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CD74HCT7046AM96 功能描述:鎖相環(huán) - PLL High Speed CMOS w/VCO & Lock Detect RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
CD74HCT7046AM96E4 功能描述:鎖相環(huán) - PLL High Speed CMOS w/VCO & Lock Detect RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
CD74HCT7046AM96G4 功能描述:鎖相環(huán) - PLL Hi Spd CMOS LogPh- Locked Loop RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
CD74HCT7046AME4 功能描述:鎖相環(huán) - PLL High Speed CMOS w/VCO & Lock Detect RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
CD74HCT7046AMG4 功能描述:鎖相環(huán) - PLL Hi Spd CMOS LogPh- Locked Loop RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
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