參數(shù)資料
型號: CD74HCT7046AM
廠商: TEXAS INSTRUMENTS INC
元件分類: XO, clock
英文描述: PHASE LOCKED LOOP, PDSO16
封裝: GREEN, PLASTIC, SOIC-16
文件頁數(shù): 2/29頁
文件大?。?/td> 485K
代理商: CD74HCT7046AM
10
SIGIN, COMPIN
DC Coupled
Low-Level Input
Voltage
VIL
-
4.5 to
5.5
-
1.35
-
1.35
-
1.35
V
LD, PCnOUT High-
Level Output Voltage
CMOS Loads
VOH
VIL or VIH
-
4.5
4.4
-
4.4
-
4.4
-
V
LD, PCnOUT High-
Level Output Voltage
TTL Loads
VOH
VIL or VIH
-
4.5
3.98
-
3.84
-
3.7
-
V
LD, PCnOUT Low-
Level Output Voltage
CMOS Loads
VOL
VIL or VIH
-
4.5
-
0.1
-
0.1
-
0.1
V
LD, PCnOUT Low-
Level Output Voltage
TTL Loads
VOL
VIL or VIH
-
4.5
-
0.26
-
0.33
-
0.4
V
SIGIN, COMPIN Input
Leakage Current
II
Any
Voltage
Between
VCC and
GND
-
5.5
-
±30
±38
±45
A
PC2OUT Three-State
Off-State Current
IOZ
VIL or VIH
-
5.5
-
±0.5
±5-
-
±10
A
SIGIN, COMPIN Input
Resistance
RI
VI at Self-Bias
Operation Point:
V, 0.5V,
See Figure 8
4.5
-
250
-
k
DEMODULATOR SECTION
Resistor Range
RS
at RS > 300k
Leakage Current
Can Influence
VDEMOUT
4.5
10
-
300
-
k
Offset Voltage VCOIN
to VDEM
VOFF
VI = VVCOIN =
Values taken over
RS Range
See Figure 15
4.5
-
±20
-
mV
Dynamic Output
Resistance at
DEMOUT
RO
VDEMOUT =
4.5
-
25
-
Quiescent Device
Current
ICC
VCC or
GND
-
5.5
-
8
-
80
-
160
A
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
ICC
(Note 4)
VCC
-2.1
(Exclud-
ing Pin 5)
-
4.5 to
5.5
-
100
360
-
450
-
490
A
NOTES:
2. The value for R1 and R2 in parallel should exceed 2.7k
; R1 and R2 values above 300k may contribute to frequency shift due to leakage
currents.
3. The maximum operating voltage can be as high as VCC -0.9V, however, this may result in an increased offset voltage.
4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
DC Electrical Specications (Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
VCC
(V)
25oC
-40oC TO 85oC -55oC TO 125oC
UNITS
VI (V)
IO (mA)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
VCC
2
VCC
2
CD74HC7046A, CD74HCT7046A
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