參數(shù)資料
型號: CDB4352
廠商: Cirrus Logic Inc
文件頁數(shù): 4/20頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR CS4352 DAC
標準包裝: 1
系列: Popguard®
DAC 的數(shù)量: 2
位數(shù): 24
采樣率(每秒): 192k
數(shù)據(jù)接口: 串行
DAC 型: 電壓
工作溫度: -40°C ~ 85°C
已供物品:
已用 IC / 零件: CS4352
產(chǎn)品目錄頁面: 757 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: CS4352-DZZR-ND - IC DAC STER 102DB 192KHZ 20TSSOP
CS4352-DZZ-ND - IC DAC STER 102DB 192KHZ 20TSSOP
CS4352-CZZR-ND - IC DAC STER 102DB 192KHZ 20TSSOP
598-1186-5-ND - IC DAC STER 102DB 192KHZ 20TSSOP
其它名稱: 598-1518
12
DS684F2
CS4352
4.3
Digital Interface Format
The device will accept audio samples in 1 of 4 digital interface formats, as illustrated in Table 5.
The desired format is selected via the DIF1 and DIF0 pins. For an illustration of the required relationship
between the LRCK, SCLK and SDIN, see Figures 3-5. For all formats, SDIN is valid on the rising edge of
SCLK. Also, SCLK must have at least 32 cycles per LRCK period in format 2 and 48 cycles per LRCK period
in format 3.
For more information about serial audio formats, refer to Cirrus Logic Application Note AN282: The 2-Chan-
nel Serial Audio Interface: A Tutorial, available at www.cirrus.com.
Table 5. Digital Interface Format
Figure 3. IS, up to 24-Bit Data
Figure 4. Right-Justified Data
Figure 5. Left-Justified up to 24-Bit Data
DIF1
DIF0
DESCRIPTION
FORMAT
FIGURE
00
IS, up to 24-bit Data
0
01
Right-Justified, 24-bit Data
1
10
Left-Justified, up to 24-bit Data
2
11
Right-Justified, 16-bit Data
3
LR C K
SCL K
Le ft C h a n n e l
Rig h t Ch an n e l
SD IN
+3 +2 +1
+5 +4
MS B
-1 -2 -3 -4 -5
+3 +2 +1
+5 +4
-1 -2 -3 -4
MS B
LS B
L RCK
SC LK
Le ft C h a n n e l
SD IN
-6 -5 -4 -3 -2 -1
-7
+1 +2 +3 +4 +5
MS B
R ig h t C ha nn el
LS B
MS B
+1 +2 +3 +4 +5
LS B
-6 -5 -4 -3 -2 -1
-7
MS B
LR C K
SC L K
Left C ha nnel
R ig h t C ha n nel
SDIN
+3 +2 +1
+5 +4
MS B
-1 -2 -3 -4 -5
+3 +2 +1
+5 +4
-1 -2 -3 -4
LSB
MSB
LS B
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