參數(shù)資料
型號: CDB4362A
廠商: Cirrus Logic Inc
文件頁數(shù): 10/13頁
文件大小: 0K
描述: BOARD EVAL FOR CS4362A DAC
標(biāo)準(zhǔn)包裝: 1
DAC 的數(shù)量: 6
位數(shù): 24
采樣率(每秒): 192k
數(shù)據(jù)接口: 串行
DAC 型: 電壓
工作溫度: -40°C ~ 85°C
已供物品:
已用 IC / 零件: CS4362A
產(chǎn)品目錄頁面: 757 (CN2011-ZH PDF)
相關(guān)產(chǎn)品: CS4362A-DQZ-ND - IC DAC 6CH 114DB 192KHZ 48-LQFP
CS4362A-CQZR-ND - IC DAC 6CH 114DB 192KHZ 48-LQFP
598-1058-ND - IC DAC 6CH 114DB 192KHZ 48LQFP
其它名稱: 598-1521
6
ICS97U870
Advance Information
0817—07/07/03
Notes:
1.
Switching characteristics guaranteed for application frequency range.
2.
Static phase offset shifted by design.
Timing Requirements
TA = 0 - 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Max clock frequency
freqop
1.8V+0.1V @ 25°C
95
370
MHz
Application Frequency
Range
freqApp
1.8V+0.1V @ 25°C
160
350
MHz
Input clock duty cycle
dtin
40
60
%
CLK stabilization
TSTAB
15
s
Switching Characteristics
1
TA = 0 - 70°C Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
Output enable time
ten
OE to any output
4.73
8
ns
Output disable time
tdis
OE to any output
5.82
8
ns
Period jitter
tjit (per)
-30
30
ps
Half-period jitter
tjit(hper)
-60
60
ps
Input Clock
1
2.5
4
v/ns
Output Enable (OE), (OS)
0.5
v/ns
Output clock slew rate
SLr1(o)
1.5
2.5
3
v/ns
tjit(cc+)
040
ps
tjit(cc-)
0
-40
ps
Dynamic Phase Offset
t( )dyn
-20
20
ps
Static Phase Offset
tSPO
2
-50
0
50
ps
tskew
40
ps
SSC modulation frequency
30.00
33
kHz
SSC clock input frequency
deviation
0.00
-0.50
%
PLL Loop bandwidth (-3 dB
from unity gain)
2.0
MHz
Cycle-to-cycle period jitter
Input slew rate
SLr1(i)
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