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參數(shù)資料
| 型號(hào)： | CDB4362A |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 6/13頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR CS4362A DAC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| DAC 的數(shù)量： | 6 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 192k |
| 數(shù)據(jù)接口： | 串行 |
| DAC 型： | 電壓 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | CS4362A |
| 產(chǎn)品目錄頁面： | 757 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | CS4362A-DQZ-ND - IC DAC 6CH 114DB 192KHZ 48-LQFP CS4362A-CQZR-ND - IC DAC 6CH 114DB 192KHZ 48-LQFP 598-1058-ND - IC DAC 6CH 114DB 192KHZ 48LQFP |
| 其它名稱： | 598-1521 |
2
ICS97U870
Advance Information
0817—07/07/03
Pin Descriptions
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The PLL clock buffer, ICS97U870, is designed for a VDDQ of 1.8 V, a AVDD of 1.8 V and differential data input and output
levels. Package options include a plastic 52-ball VFBGA and a 40-pin MLF.
ICS97U870 is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to ten differential
pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock outputs (FB_OUTT, FBOUTC).
The clock outputs are controlled by the input clocks (CLK_INT, CLK_INC), the feedback clocks (FB_INT, FB_INC), the
LVCMOS program pins (OE, OS) and the Analog Power input (AVDD).When OE is low, the outputs (except FB_OUTT/
FB_OUTC) are disabled while the internal PLL continues to maintain its locked-in frequency. OS (Output Select) is a
program pin that must be tied to GND or VDDQ.When OS is high, OE will function as described above.When OS is low,
OE has no effect on CLKT7/CLKC7 (they are free running in addition to FB_OUTT/FB_OUTC).When AVDD is grounded,
the PLL is turned off and bypassed for test purposes.
When both clock signals (CLK_INT, CLK_INC) are logic low, the device will enter a low power mode. An input logic
detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform
a low power state where all outputs, the feedback and the PLL are OFF.When the inputs transition from both being logic
low to being differential signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL
will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input clock pair (CLK_INT, CLK_INC)
within the specified stabilization time tSTAB.
The PLL in ICS97U870 clock driver uses the input clocks (CLK_INT, CLK_INC) and the feedback clocks (FB_INT,
FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT[0:9], CLKC[0:9]).ICS97U870
is also able to track Spread Spectrum Clocking (SSC) for reduced EMI.
ICS97U870 is characterized for operation from 0°C to 70°C.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| CDB4364 | 功能描述:音頻 IC 開發(fā)工具 Eval Bd 6-Ch DAC w/DSD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評(píng)估:TAS5614L 工作電源電壓:12 V to 38 V |
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