參數(shù)資料
型號(hào)： CDB4382A
廠商： Cirrus Logic Inc
文件頁(yè)數(shù)： 32/50頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR CS4382A DAC
標(biāo)準(zhǔn)包裝： 1
DAC 的數(shù)量： 8
位數(shù)： 24
采樣率（每秒）： 192k
數(shù)據(jù)接口： 串行
DAC 型： 電壓
工作溫度： -40°C ~ 85°C
已供物品： 板
已用 IC / 零件： CS4382A
產(chǎn)品目錄頁(yè)面： 757 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： CS4382A-DQZR-ND - IC DAC 8CH 114DB 192KHZ 48-LQFP
CS4382A-DQZ-ND - IC DAC 8CH 114DB 192KHZ 48-LQFP
CS4382A-CQZR-ND - IC DAC 8CH 114DB 192KHZ 48-LQFP
598-1061-ND - IC DAC 8CH 114DB 192KHZ 48LQFP
其它名稱： 598-1524
38
DS618F2
CS4382A
from mute to the original volume value after a filter-mode change according to the settings of the Soft and
Zero Cross bits in the Mode Control 3 register. When disabled, an immediate mute and unmute is per-
formed.
Loss of clocks or a change in the FM bits will always cause an immediate mute; unmute in these condi-
tions is affected by the RMP_UP bit.
Note:
For best results, it is recommended that this feature be used in conjunction with the RMP_UP bit.
6.5
Invert Control (Address 05h)
6.5.1
Invert Signal Polarity (Inv_Xx)
Default = 0
0 - Disabled
1 - Enabled
Function:
When enabled, these bits will invert the signal polarity of their respective channels.
6.6
Mixing Control Pair 1 (Channels A1 & B1)(Address 06h)
Mixing Control Pair 2 (Channels A2 & B2)(Address 09h)
Mixing Control Pair 3 (Channels A3 & B3)(Address 0Ch)
Mixing Control Pair 4 (Channels A4 & B4)(Address 0Fh)
6.6.1
Channel A Volume = Channel B Volume (A=B)
Default = 0
0 - Disabled
1 - Enabled
Function:
The AOUTAx and AOUTBx volume levels are independently controlled by the A and the B Channel Vol-
ume Control Bytes when this function is disabled. The volume on both AOUTAx and AOUTBx are deter-
mined by the A Channel Attenuation and Volume Control Bytes (per A-B pair), and the B Channel Bytes
are ignored when this function is enabled.
76
543
21
0
INV_B4
INV_A4
INV_B3
INV_A3
INV_B2
INV_A2
INV_B1
INV_A1
00
000
00
0
76
543
21
0
Px_A=B
PxATAPI4
PxATAPI3
PxATAPI2
PxATAPI1
PxATAPI0
PxFM1
PxFM0
00
100
10
0
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