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參數(shù)資料
| 型號： | CDB8421 |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 14/17頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR CS8421 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 音頻，采樣率轉(zhuǎn)換器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | CS8421，CS8406，CS8416 |
| 主要屬性： | 帶數(shù)字音頻發(fā)射器和接收器的采樣率轉(zhuǎn)換器 |
| 次要屬性： | S/PDIF 接口 |
| 已供物品： | 板，CD |
| 產(chǎn)品目錄頁面： | 759 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | 598-1730-ND - IC SAMPLE RATE CONVERTER 20QFN 598-1126-5-ND - IC SAMPLE RATE CONVERTER 20TSSOP |
| 其它名稱： | 598-1018 |
6
DS641F6
CS8421
Pin Name
#
Pin Description
XTO
1
Crystal Out (Output) - Crystal output for Master clock. See “Master Clock” on page 20.
XTI
2
Crystal/Oscillator In (Input) - Crystal or digital clock input for Master clock. See “Master Clock”
VD
3
Digital Power (Input) - Digital core power supply. Typically +2.5 V.
GND
4
Ground (Input) - Ground for I/O and core logic.
RST
5
Reset (Input) - When RST is low, the CS8421 enters a low-power mode and all internal states are
reset. On initial power-up, RST must be held low until the power supply is stable and all input
clocks are stable in frequency and phase.
BYPASS
6
Sample Rate Converter Bypass (Input) - When BYPASS is high, the sample rate converter will
be bypassed, and any data input through the serial audio input port will be directly output on the
serial audio output port. When BYPASS is low, the sample rate converter will operate normally.
ILRCK
7
Serial Audio Input Left/Right Clock (Input/Output) - Word-rate clock for the audio data on the
SDIN pin.
ISCLK
8
Serial Audio Bit Clock (Input/Output) - Serial-bit clock for audio data on the SDIN pin.
SDIN
9
Serial Audio Input Data Port (Input) - Audio data serial input pin.
MCLK_OUT
10
Master Clock Output (Output) - Buffered and level-shifted output for Master clock. If MCLK_OUT
is not required, this pin should be pulled high through a 47 k
resistor to turn the output off. See
TDM_IN
11
Serial Audio TDM Input (Input) - Time Division Multiplexing serial audio data input. Grounded
when not used. See “Time Division Multiplexing (TDM) Mode” on page 21.
SDOUT
12
Serial Audio Output Data Port (Output) - Audio data serial output pin. Optionally, this pin may be
pulled low through a 47-k
resistor, but must not be pulled high.
OSCLK
13
Serial Audio Bit Clock (Input/Output) - Serial-bit clock for audio data on the SDOUT pin.
OLRCK
14
Serial Audio Input Left/Right Clock (Input/Output) - Word-rate clock for the audio data on the
SDOUT pin.
MS_SEL
15
Master/Slave Select (Input) - Used to select Master or Slave for the input and output serial audio
ports at startup and reset. See Table 1 on page 18 for settings.
GND
16
Ground (Input) - Ground for I/O and core logic.
VL
17
Logic Power (Input) - Input/Output power supply. Typically +3.3 V or +5.0 V.
SAOF
18
Serial Audio Output Format Select (Input) - Used to select the serial audio output format at
startup and reset. See Table 3 on page 18 for format settings.
SAIF
19
Serial Audio Input Format Select (Input) - Used to select the serial audio input format at startup
and reset. See Table 2 on page 18 for format settings.
SRC_UNLOCK
20
SRC Unlock Indicator (Output) - Indicates when the SRC is unlocked. See “SRC Locking and
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