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參數資料
| 型號： | CDB8421 |
| 廠商： | Cirrus Logic Inc |
| 文件頁數： | 9/17頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR CS8421 |
| 標準包裝： | 1 |
| 主要目的： | 音頻，采樣率轉換器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | CS8421，CS8406，CS8416 |
| 主要屬性： | 帶數字音頻發(fā)射器和接收器的采樣率轉換器 |
| 次要屬性： | S/PDIF 接口 |
| 已供物品： | 板，CD |
| 產品目錄頁面： | 759 (CN2011-ZH PDF) |
| 相關產品： | 598-1730-ND - IC SAMPLE RATE CONVERTER 20QFN 598-1126-5-ND - IC SAMPLE RATE CONVERTER 20TSSOP |
| 其它名稱： | 598-1018 |
DS641F6
17
CS8421
4.2
Mode Selection
The CS8421 uses the resistors attached to the MS_SEL, SAIF, and SAOF pins to determine the modes of operation.
After reset, the resistor value and condition (VL or GND) are sensed. This operation will take approximately 4
s to
complete. The SRC_UNLOCK pin will remain high and the SDOUT pin will be muted until the mode detection se-
quence has completed. After this, if all clocks are stable, SRC_UNLOCK will be brought low when audio output is
valid and normal operation will occur. Tables 1, 2, and 3 show the pin functions and their corresponding settings. If
the 1.0 k
option is selected for MS_SEL, SAIF, or SAOF, the resistor connected to that pin may be replaced by a
direct connection to VL or GND as appropriate.
The resistor attached to each mode-selection pin should be placed physically close to the CS8421. The end of the
resistor not connected to the mode selection pins should be connected as close as possible to VL and GND to min-
imize noise. Tables 1, 2, and 3 show the pin functions and their corresponding settings.
I/OLRCK
I/OSCLK
MS B
LS B
MS B
LS B
Channel A
SDIN
SDOUT
MSB
Channel B
Figure 7. Serial Audio Interface Format - IS
MS B
LS B
MS B
LS B
MSB
I/OLRCK
I/OSCLK
SDIN
SDOUT
Channel A
Channel B
Figure 8. Serial Audio Interface Format - Left-Justified
I/OLRCK
I/OSCLK
Channel A
SDIN
Channel B
MSB
SDOUT
MSB
LSB
MSB Extended
Figure 9. Serial Audio Interface Format - Right-Justified
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