VDD = 5V, V
參數(shù)資料
型號: CDP68HC68T1M2Z96
廠商: Intersil
文件頁數(shù): 18/23頁
文件大?。?/td> 0K
描述: IC RTC RAM/SPI SERIAL 16-SOIC
標準包裝: 1,000
類型: 時鐘/日歷
特點: 警報器,閏年,方波輸出,監(jiān)視計時器
存儲容量: 32B
時間格式: HH:MM:SS(12/24 小時)
數(shù)據(jù)格式: YY-MM-DD-dd
接口: SPI
電源電壓: 3 V ~ 6 V
電壓 - 電源,電池: 2.2 V ~ 6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-SOIC(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 16-SOIC
包裝: 帶卷 (TR)
4
FN1547.8
October 29, 2007
Operating Current (Note 3)
VDD = 5V, VB = 3V
Crystal Operation
ID
IB
-mA
32kHz
-
0.025
0.015
-
mA
1MHz
-
0.08
0.15
-
mA
2MHz
-
0.15
0.25
-
mA
4MHz
-
0.3
0.4
-
mA
Standby Current (Note 3)
VB = 2.2V
Crystal Operation
IB
32kHz
-
10
-
A
Input Capacitance
CIN
VIN = 0, TA = +25°C
-
2
pF
Maximum Rise and Fall Times
(Except XTAL Input and POR Pin 10)
tr, tf
--
2
s
--
s
Input Voltage (Line Input Pin Only, Power Sense
Mode)
010
12
V
VSYS > VBVT
(For VB Not Internally Connected to VDD)
-1.0
-
V
Power-On Reset (POR) Pulse Width
100
75
-
ns
NOTES:
2. Typical values are for TA = +25°C and nominal VDD.
3. Clock out (Pin 1) disabled, outputs open circuited. No serial access cycles.
Dynamic Electrical Specifications
Bus Timing VDD ±10%, VSS = 0VDC, TA = -40°C to +85°C
IDENTIFICATION
NUMBER
PARAMETER
SYMBOL
LIMITS (ALL TYPES)
UNITS
VDD = 3.3V
VDD = 5V
MIN
MAX
MIN
MAX
1
Chip Enable Setup Time
tEVCV
200
-
100
-
ns
2
Chip Enable After Clock Hold Time
tCVEX
250
-
125
-
ns
3
Clock Width High
tWH
400
-
200
-
ns
4
Clock Width Low
tWL
400
-
200
-
ns
5
Data In to Clock Setup Time
tDVCV
200
-
100
-
ns
7
Clock to Data Propagation Delay
tCVDV
-
200
-
100
ns
8
Chip Disable to Output High Z
tEXQZ
-
200
-
100
ns
11
Output Rise Time
tr
-
200
-
100
ns
12
Output Fall Time
tf
-
200
-
100
ns
A
Data in After Clock Hold Time
tCVDX
200
-
100
-
ns
B
Clock to Data Out Active
tCVQX
-
200
-
100
ns
C
Clock Recovery Time
tREC
200
-
200
-
ns
Static Electrical Specifications At TA = -40°C to +85°C, VDD = VBATT = 5V ±5%, Unless Otherwise Specified. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
CDP68HC68T1
UNITS
MIN
TYP
(Note 2)
MAX
CDP68HC68T1
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