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參數(shù)資料
| 型號： | CDP68HC68T1MZ96 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 6/23頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC RAM/SPI SERIAL 20-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 時鐘/日歷 |
| 特點： | 警報器，閏年，方波輸出，監(jiān)視計時器 |
| 存儲容量： | 32B |
| 時間格式： | HH:MM:SS（12/24 小時） |
| 數(shù)據(jù)格式： | YY-MM-DD-dd |
| 接口： | SPI |
| 電源電壓： | 3 V ~ 6 V |
| 電壓 - 電源，電池： | 2.2 V ~ 6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC W |
| 包裝： | 帶卷 (TR) |
14
FN1547.8
October 29, 2007
Functional Description
The Serial Peripheral Interface (SPI) utilized by the
CDP68HC68T1 is a serial synchronous bus for address and
data transfers. The clock, which is generated by the
microcomputer is active only during address and data
transfers. In systems using the CDP68HC05C4 or
CDP68HC05D2, the inactive clock polarity is determined by
the CPOL bit in the microcomputer’s Control Register. A
unique feature of the CDP68HC68T1 is that it automatically
determines the level of the inactive clock by sampling SCK
when CE becomes active (see Figure 8). Input data (MOSI)
is latched internally on the internal strobe edge and output
data (MISO) is shifted out on the shift edge, as defined by
Figure 8. There is one clock for each data bit transferred
(address, as well as data bits are transferred in groups of 8).
Address and Data Format
There are three types of serial transfer:
1. Address Control - Figure 9.
2. READ or WRITE Data - Figure 10.
3. Watchdog Reset (actually a non-transfer) Figure 11.
The Address/Control and Data bytes are shifted MSB first,
Into the serial data input (MOSI) and out of the serial data
output (MISO).
Any transfer of data requires an Address/Control byte to
specify a Write or Read operation and to select a Clock or
RAM location, followed by one or more bytes of data.
Data is transferred out of MISO for a Read and into MOSI for
a Write operation.
Address/Control Byte - (see Figure 9)
It is always the first byte received after CE goes true. To
transmit a new address, CE must first go false and then true
again. Bit 5 is used to select between Clock and RAM
locations.
SHIFT
INTERNAL
STROBE
INTERNAL
STROBE
SHIFT
CE
SCK
CPOL = 1
SCK
CE
CPOL = 0
MOSI
MSB
MSB -1
NOTE: “CPOL” is a bit that is set in the microcomputer’s Control
Register.
FIGURE 8. SERIAL RAM CLOCK (SCK) AS A FUNCTION OF
MCU CLOCK POLARITY (CPOL)
BIT
7
6
5
4
3
2
1
0
W/R
0
CLK RAM
A4
A3
A2
A1
A0
04
A0 through A4
Selects 5-bit HEX Address of RAM or specifies Clock Register. Most Significant Address
Bit. If equal to “1”, A0 through A4 selects a Clock Register. If equal to “0”, A0 through A4
selects one of 32 RAM locations. Must be set to ”0” when not in Test Mode 7W/R W/R = “1”
initiates one or more WRITE cycles.W/R = “0”, initiates one or more READ cycles.
5CLK RAM
60
7W/R
NOTE: SCK can be either polarity.
FIGURE 9. ADDRESS/CONTROL BYTE-TRANSFER WAVEFORMS
A2
A1
A0
A3
A4
CLOCK
0
W/R
MOSI
RAM
SCK (NOTE)
CE
CDP68HC68T1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDP68HC68T1W | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Serial Real-Time Clock With RAM and Power Sense/Control |
| CDP68HC68T1W WAF | 制造商:Harris Corporation 功能描述: |
| CDP68HC68T2D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Real-Time Clock |
| CDP68HC68T2E | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Real-Time Clock |
| CDP68HC68T2M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Real-Time Clock |
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