參數資料
| 型號： | CDP68HC68T1MZ |
| 廠商： | Intersil |
| 文件頁數： | 13/23頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RTC RAM/SPI SERIAL 20-SOIC |
| 標準包裝： | 38 |
| 類型： | 時鐘/日歷 |
| 特點： | 警報器，閏年，方波輸出，監(jiān)視計時器 |
| 存儲容量： | 32B |
| 時間格式： | HH:MM:SS（12/24 小時） |
| 數據格式： | YY-MM-DD-dd |
| 接口： | SPI |
| 電源電壓： | 3 V ~ 6 V |
| 電壓 - 電源，電池： | 2.2 V ~ 6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 20-SOIC W |
| 包裝： | 管件 |
20
FN1547.8
October 29, 2007
Example of an automotive system. The VSYS and LINE inputs can be used to sense the ignition turning on and off. An
external switch is included to activate the system without turning on the ignition. Also, the CMOS CPU is not powered down
with the system VDD, but is held in a low power reset mode during power down. When restoring power the CDP68HC68T1
will enable the CLK OUT pin and set the PSE and CPUR high.
Important Application Note: Those units with a code of 6PG have delayed alarm interrupts of 8.3ms regardless of
CDP68HC68T1’s operating frequency. (See "Functional Description", INT on page 10.) In addition, reading the Status
Register before delayed alarm activates will disable alarm signal.
FIGURE 19. AUTOMOTIVE SYSTEM DIAGRAM
System Diagrams (Continued)
XTAL
LINE
VDD
VSYS
VBATT
POR
2MHz
PSE
CPUR
CLK OUT
SPI
CE
INT
T1
VSS
VDD
RESET
OSC1
IRQ
SPI
PORT
CDP68HC05C4B
VSS
PORT
5V
REG
+
-
12V
IGNITION
3
CLOCK BUTTON
ENABLED POWER
CDP68HC68T1
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CDP68HC68T1MZ96 | 功能描述:實時時鐘 W/ANEAL PERIPH SPIAL -TIME-CLK 20W IND RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時間格式:HH:MM:SS RTC 存儲容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| CDP68HC68T1W | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS Serial Real-Time Clock With RAM and Power Sense/Control |
| CDP68HC68T1W WAF | 制造商:Harris Corporation 功能描述: |
| CDP68HC68T2D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Real-Time Clock |
| CDP68HC68T2E | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Real-Time Clock |
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