Power Sensing (See Figure 3) When Power Sensing is enabled (Bit 5 = 1 in In" />
參數(shù)資料
型號(hào)： CDP68HC68T1MZ
廠商： Intersil
文件頁(yè)數(shù)： 23/23頁(yè)
文件大?。?/td> 0K
描述： IC RTC RAM/SPI SERIAL 20-SOIC
標(biāo)準(zhǔn)包裝： 38
類(lèi)型： 時(shí)鐘/日歷
特點(diǎn)： 警報(bào)器，閏年，方波輸出，監(jiān)視計(jì)時(shí)器
存儲(chǔ)容量： 32B
時(shí)間格式： HH:MM:SS（12/24 小時(shí)）
數(shù)據(jù)格式： YY-MM-DD-dd
接口： SPI
電源電壓： 3 V ~ 6 V
電壓 - 電源，電池： 2.2 V ~ 6 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 20-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 20-SOIC W
包裝： 管件
9
FN1547.8
October 29, 2007
Power Sensing (See Figure 3)
When Power Sensing is enabled (Bit 5 = 1 in Interrupt
Control Register), AC transitions are sensed at the LINE input
pin. Threshold detectors determine when transitions cease.
After a delay of 2.68ms to 4.64ms, plus the external input
circuit RC time constant, an interrupt is generated and a bit is
set in the Status Register. This bit can then be sampled to see
if system power has turned back on. See "Functional
Description", Line pin on page 10. The power-sense circuitry
operates by sensing the level of the voltage presented at the
line input pin. This voltage is centered around VDD and as
long as it is either plus or minus a threshold (about 1V) from
VDD a power-sense failure will not be indicated. With an AC
signal present, remaining in this VDD window longer than a
minimum of 2.68ms will activate the power-sense circuit. The
larger the amplitude of the AC signal, the less time it spends
in the VDD window, and the less likely a power failure will be
detected. A 60Hz, 10VP-P sinewave voltage is an applicable
signal to present at the LINE input pin to setup the power
sense function.
Power-Down (See Figure 4)
Power-down is a processor-directed operation. A bit is set in
the Interrupt Control Register to initiate operation. Three pins
are affected. The PSE (Power Supply Enable) output,
normally high, is placed low. The CLK OUT is placed low.
The CPUR output, connected to the processors reset input
is also placed low. In addition, the Serial Interface is
disabled.
Power-Up (See Figures 5 and 6)
Two conditions will terminate the Power-Down mode.
1. The first condition (see Figure 5) requires an interrupt.
The interrupt can be generated by the alarm circuit, the
programmable periodic interrupt signal, or the power
sense circuit.
FIGURE 3. POWER-SENSING FUNCTIONAL DIAGRAM
FIGURE 4. POWER-DOWN FUNCTIONAL DIAGRAM
FIGURE 5. POWER-UP FUNCTIONAL DIAGRAM (INITIATED
BY INTERRUPT SIGNAL
XTAL IN
XTAL OUT
LINE
VDD
REAL-TIME CLOCK
CDP68HC68T1
STATUS REGISTER
INT
CPU
CDP68HC05C16B
VDD
0V
I
VSYS
INTERRUPT
CONTROL
REGISTER
I
SERIAL
INTERFACE
CLK
OUT
CPUR
REAL-TIME CLOCK
CDP68HC68T1
PSE
OSC
RESET
CPU
CDP68HC05C4B
MISO
MOSI
FROM SYSTEM
POWER
TO SYSTEM
POWER CONTROL
POWER
SENSE
OR
ALARM
CIRCUIT
SERIAL
INTERFACE
PERIODIC
INTERRUPT
SIGNAL
POWER-UP
REAL-TIME CLOCK
CDP68HC68T1
PSE
CPUR
CLK
OUT
INT
MISO
MOSI
CDP68HC68T1
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CDP68HC68T1MZ96 功能描述:實(shí)時(shí)時(shí)鐘 W/ANEAL PERIPH SPIAL -TIME-CLK 20W IND RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線(xiàn)接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube
CDP68HC68T1W 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:CMOS Serial Real-Time Clock With RAM and Power Sense/Control
CDP68HC68T1W WAF 制造商:Harris Corporation 功能描述:
CDP68HC68T2D 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Real-Time Clock
CDP68HC68T2E 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Real-Time Clock
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