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18
201-0000-032 Rev 3.0, 6/2/99
CHRONTEL
CH5001A
Mode / Output Format Register
Symbol: MOF
Address: 00h
Bits: 8
Register MOF determines the operating mode of the IC, output data format and the chrominance sample location.
When bit 0 of register OF is low, data will be output in 16-bit mode. When OF is high, data will be time multiplexed
and output on the 8-bit bus Y[7:0]. In the tables below, Y0 is the first pixel generated from the array on a given line,
Y1 is the second pixel on that line, etc. In CCIR modes, Y0i, Y1i data are the pixels interpolated between the Y0 and
Y1, and Y1 and Y2 samples. For each of the possible modes, the format of the output data is shown below. The total
amount of time shown for each table is 24 cycles of MCLK when ELFA=0 and 48 cycles of MCLK when ELFA=1.
The line number in each table refers to which active video line is being output.
M[2:0] = 0 or 1, OF = 0, CIF2 = 0 (2 line pattern, CLKOUT = 6.75MHz (ELFA=0) or 3.375MHz (ELFA=1))
M[2:0] = 0 or 1, OF = 1, CIF2 = 0 (2 line pattern, CLKOUT = 13.5 MHz (ELFA=0) or 6.75MHz (ELFA=1))
M[2:0] = 0 or 1, OF = 0, CIF2 = 1 (1 line pattern, CLKOUT = 6.75MHz (ELFA=0) or 3.375MHz (ELFA=1))
M[2:0] = 0 or 1, OF = 1, CIF2 = 1 (1 line pattern, CLKOUT = 13.5 MHz (ELFA=0) or 6.75MHz (ELFA=1)
)
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
TYPE:
CIF2
ELFA
CVL
CHL
M2
M1
M0
OF
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DEFAULT:
0
0
0
0
1
0
PUD6
1
Line
CLKOUT
1
2
3
4
5
6
1
Y[7:0]
Y0
Y1
Y2
Y3
Y4
Y5
1
C[7:0]
128
128
128
128
128
128
2
Y[7:0]
Y0
Y1
Y2
Y3
Y4
Y5
2
C[7:0]
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
Line
CLKOUT
1
2
3
4
5
6
7
8
9
10
11
12
1
Y[7:0]
128
Y0
128
Y1
128
Y2
128
Y3
128
Y4
128
Y5
2
Y[7:0]
Cb0
Y0
Cr0
Y1
Cb2
Y2
Cr2
Y3
Cb4
Y4
Cr4
Y5
Line
CLKOUT
1
2
3
4
5
6
1
Y[7:0]
Y0
Y1
Y2
Y3
Y4
Y5
1
C[7:0]
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
2
Y[7:0]
Y0
Y1
Y2
Y3
Y4
Y5
2
C[7:0]
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
Line
CLKOUT
1
2
3
4
5
6
7
8
9
10
11
12
1
Y[7:0]
Cb0
Y0
Cr0
Y1
Cb2
Y2
Cr2
Y3
Cb4
Y4
Cr4
Y5
2
Y[7:0]
Cb0
Y0
Cr0
Y1
Cb2
Y2
Cr2
Y3
Cb4
Y4
Cr4
Y5