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CHRONTEL
CH5001A
201-0000-032 Rev 3.0, 6/2/99
23
6
ESLH6
Vertical Start Register
Symbol:VS
Address:03h
Bits:6
Register VS determines the number of lines between the leading edge of V Sync and the first active line to be output
on the Y[7:0] and C[7:0] pins. The number is in units of lines; the range is 0 to 31 lines. When ELFA = 1, this
register is ignored, and there is always a one line delay between the leading edge of vertical sync and the first line
with active video.
The YDEL (bit 6) controls the delay in the luma processing path. The value should match the setting of CHL.
Electronic Shutter Length High Byte
Symbol:ESLH
Address:04h
Bits:8
The ESLH register, combined with the ESLE and ESLL registers determine the length of the electronic shutter.
Electronic Shutter Length Low Byte
Symbol:ESLL
Address:05h
Bits:8
Registers ESLE, ESLH and ESLL specify the duration of the electronic shutter. These 21 bits are concatenated into
a single 21-bit word ({ESLE,ESLH,ESLL}) whose value is multiplied by 8. The shutter is enabled for this number
of MCLKs. The duration of the shutter can, therefore, be determined from the equation (8*(65536*ESLE +
256*ESLH + ESLL))/MCLK. The range is from 0mS to 699mS, but is limited to a lower value in some frame rates
(see Frame Rate Register description). When the autoshutter algorithm is controlling the shutter value and this
register is read out, the autoshutter generated value is read instead of the actual IIC register content.
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
TYPE:
YDEL
VS4
VS3
VS2
VS1
VS0
R/W
R/W
R/W
R/W
R/W
R/W
DEFAULT:
0
1
0
1
0
1
BIT:
SYMBOL:
7
5
4
3
2
1
0
ESLH7
ESLH5
ESLH4
ESLH3
ESLH2
ESLH1
ESLH0
TYPE:
DEFAULT:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
1
1
0
0
0
0
BIT:
SYMBOL:
7
6
5
4
3
2
1
0
ESLL7
ESLL6
ESLL5
ESLL4
ESLL3
ESLL2
ESLL1
ESLL0
TYPE:
DEFAULT:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0