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參數(shù)資料
| 型號(hào)： | CH5101A-Q |
| 廠(chǎng)商： | Electronic Theatre Controls, Inc. |
| 英文描述： | CMOS Monochrome Digital Video Camera |
| 中文描述： | 單色的CMOS數(shù)碼攝像機(jī) |
| 文件頁(yè)數(shù)： | 24/32頁(yè) |
| 文件大?。?/td> | 132K |
| 代理商： | CH5101A-Q |
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24
201-0000-033 Rev 1.0, 6/2/99
CHRONTEL
CH5101A
Bits 2 and 3 (HSP and VSP) of the MISC register control the polarity of the H and V sync signals.
Bit 4 (PD) of the MISC register places the IC in a power down mode. When PD=1, clocks to all digital circuitry are
disabled and analog circuitry bias currents are shut down. When PD=0, the IC is placed in its normal operating
mode according to the user inputs. The default value of this bit is set using the PUD5 input.
Bit 5 (DVDD) of the MISC register is a reserved bit for memory control.
Device ID Register
Symbol:DID
Address:1Ah
Bits:8
Register DID is a read only register which holds the device ID number of the CH5101.
Test Register
Symbol:TST
Address:1Bh
Bits:8
TST is a test register.
Test Memory Register
Symbol:TM
Address:1Ch
Bits:8
TM is a test register.
Table 11. Border Colors
BDR
1
BDR
0
Color
Y
Value
CR
Value
CB
Value
0
0
Black
16
128
128
0
1
Blue
40
110
240
1
0
Green
144
33
53
1
1
White
235
128
128
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
TYPE:
DID7
DID6
DID5
DID4
DID3
DID2
DID1
DID0
R
R
R
R
R
R
R
R
DEFAULT:
0
0
1
0
0
0
0
0
BIT:
SYMBOL:
7
6
5
4
3
2
1
0
LM Done
LS Select
LM Test
IOC1
IOC0
CSH2
CSH1
CSH0
TYPE:
DEFAULT:
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT:
SYMBOL:
7
6
5
4
3
2
1
0
TM7
TM6
TM5
TM4
TM3
TM2
TM1
TM0
TYPE:
DEFAULT:
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
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