參數(shù)資料
型號(hào): CH7003B-T
廠商: Electronic Theatre Controls, Inc.
英文描述: Digital PC to TV Encoder
中文描述: 數(shù)碼電腦電視編碼器
文件頁(yè)數(shù): 29/50頁(yè)
文件大?。?/td> 334K
代理商: CH7003B-T
CHRONTEL
CH7003B
201-0000-023 Rev 4.1, 8/2/99
29
Registers and Programming
The CH7003 is a fully programmable device, providing for full functional control through a set of registers accessed
from the I
2
C port. The CH7003 contains a total of 31 registers, which are listed in
Table 15
and described in detail
under
Register Descriptions
. Detailed descriptions of operating modes and their effects are contained in the previous
section,
Functional Description.
An addition (+) sign in the Bits column below signifies that the parameter contains
more than 8 bits, and the remaining bits are located in another register.
Table 15. Register Map
Register
Symbol
DMR
FFR
VBW
Address
00H
01H
03H
Bits
Functional Summary
Display mode selection
Flicker filter mode selection
Luma and chroma filter bandwidth
selection
Data format and bit-width selections
Display Mode
Flicker Filter
Video Bandwidth
8
2
7
Input Data Format
Clock Mode
IDF
CM
04H
06H
6
7
Sets the clock mode to be used
Start Active Video
SAV
07H
8+
Active video delay setting
Position Overflow
PO
08H
3
MSB bits of position values
Black level adjustment
Input latch clock edge select
Enables horizontal movement of
displayed image on TV
Black Level
BLR
09H
8
Horizontal Position
Vertical Position
HPR
0AH
8+
VPR
0BH
8+
Enables vertical movement of displayed
image on TV
Determines the horizontal and vertical
sync polarity
Enables power saving modes
Detection of TV presence
Contrast enhancement setting
Contains the MSB bits for the M and N
PLL values
Sets the PLL M value - bits (7:0)
Sets the PLL N value - bits (7:0)
Determines the clock output at pin 41
Determines the subcarrier frequency
Sync Polarity
Power Management
Connection Detect
Contrast Enhancement
PLL M and N
extra bits
PLL-M Value
PLL-N Value
Buffered Clock
Subcarrier Frequency
Adjust
PLL and Memory
Control
CIV Control
Calculated Fsc
Increment Value
Version ID
Test
SPR
0DH
4
PMR
CDR
CE
MNE
0EH
10H
11H
13H
5
4
3
5
PLLM
PLLN
BCO
FSCI
14H
15H
17H
18H - 1FH
8+
8+
6
4 each
PLLC
20H
6
Controls for the PLL and memory
sections
Control of CIV value
Readable register containing the
calculated subcarrier increment value
Device version number
Reserved for test (details not included
herein)
Current register being addressed
CIVC
CIV
21H
22H - 24H
3
8 each
VID
TR
25H
26H - 29H
5
30
Address
AR
2AH
6
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