參數(shù)資料
型號(hào): CH7006C
廠商: Electronic Theatre Controls, Inc.
英文描述: MODULE
中文描述: 數(shù)字電視編碼器電腦功能
文件頁(yè)數(shù): 38/49頁(yè)
文件大?。?/td> 338K
代理商: CH7006C
CHRONTEL
CH7006C
38
201-0000-026 Rev 2.1, 8/2/99
Register Descriptions
(continued)
Power Management Register
Symbol: PMR
Address: 0EH
Bits: 5
This register provides control of the power management functions, a software reset (ResetB), and the SCART
output enable. The CH7006 provides programmable control of its operating states, as described in the table below.
Reset* (bit 3) is soft reset. Setting this bit will reset all circuitry requiring a power on reset, except for this bit itself
and the I
2
C state machines.
SCART (bit 4) is the SCART enable. Setting SCART = 0 means the CH7006 will operate normally, outputting Y/C
and CVBS from the three DACs. SCART=1 enables SCART output, which will cause R, G and B to be output from
the DACs and composite sync from the CSYNC pin.
Note:
For complete details regarding the operation of these modes, see the
Power Management
in
Functional Description
sections.
Connection Detect Register
Symbol: CDR
Address: 10H
Bits: 4
The Connection Detect Register provides a means to sense the connection of a TV to either S-Video or Composite
video outputs. The status bits, YT, CT, and CVBST correspond to the DAC outputs for S-Video (Y and C outputs)
and Composite video (CVBS), respectively. However, the values contained in these status bits are NOT VALID
until a sensing procedure is performed. Use of this register requires a sequence of events to enable the sensing of
outputs, then reading out the applicable status bits. The detection sequence works as follows:
1. Ensure the power management register Bits 2-0 is set to 011 (normal mode).
Bit:
Symbol:
7
6
5
4
SCART
3
Reset*
2
PD2
1
PD1
0
PD0
Type:
Default:
R/W
R/W
R/W
R/W
R/W
0
1
0
1
1
Table 22. Power Management
PD[2:0]
Operating State
Composite Off
Power Down
Functional Description
000
001
CVBS DAC is powered down.
Most pins and circuitry are disabled (except for the buffered clock outputs
which are limited to the 14MHz output and VCO divided output when the
DS/BCO pin is selected to be an output).
S-Video DACs are powered down.
All circuits and pins are active.
All circuitry is powered down except I
2
C circuit.
010
011
1XX
S-Video Off
Normal (On)
Full Power Down
Bit:
7
6
5
4
3
YT
2
CT
1
CVBST
0
SENSE
Symbol:
Type:
R
R
R
W
Default:
0
0
0
0
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