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參數(shù)資料
| 型號(hào)： | CH7013A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Digital PC to TV Encoder |
| 中文描述： | 數(shù)碼電腦電視編碼器 |
| 文件頁數(shù)： | 30/46頁 |
| 文件大小： | 249K |
| 代理商： | CH7013A |
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CHRONTEL
CH7013A
30
201-0000-041 Rev. 1.0, 6/14/2000
Register Descriptions
(continued)
Input Data Format Register
Symbol: IDF
Address: 04H
Bits: 6
This register sets the variables required to define the incoming pixel data stream.
RGBBP (bit 5): Setting this bit enables the RGB pass-through mode. Setting this bit to a 1 causes the input RGB
signal to be directly output at the DACs (subject to a pipeline delay). If RGBBP=0, the bypass mode is disabled.
DACG (bit 6): This bit controls the gain of the D/A converters. When DACG=0, the nominal DAC current is 71
μ
A, which provides the correct levels for NTSC and PAL-M. When DACG=1, the nominal DAC current is 76
μ
A,
which provides the correct levels for PAL and NTSC-J.
Clock Mode Register
Symbol: CM
Address: 06H
Bits: 8
The setting of the clock mode bits determines the clocking mechanism used in the CH7013A. The clock modes are
shown in the table below. PCM controls the frequency of the pixel clock, and XCM identifies the frequency of the
XCLK input clock.
Bit:
Symbol:
Type:
Default:
7
6
5
4
3
2
1
0
DACG
RGBBP
IDF3
IDF2
IDF1
IDF0
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Table 21. Input Data Format
IDF[3:0]
Description
0000
0001
0010
16-bit non-multiplexed RGB (16-bit color, 565) input
16-bit non-multiplexed YCrCb (24-bit color) input (Y non-multiplexed, CrCb multiplexed
16-bit multiplexed RGB (24-bit color) input
0011
0100
0101
15-bit non-multiplexed RGB (15-bit color, 555) input
12-bit multiplexed RGB (24-bit color) input (“C” multiplex scheme)
12-bit multiplexed RGB2 (24-bit color) input (“I” multiplex scheme)
0110
0111
1000
8-bit multiplexed RGB (24-bit color, 888) input
8-bit multiplexed RGB (16-bit color, 565) input
8-bit multiplexed RGB (15-bit color, 555) input
1001-1111
8-bit multiplexed YCrCb (24-bit color) input (Y, Cr and Cb are multiplexed)
Bit:
Symbol:
Type:
Default:
7
CFRB
6
M/S*
5
Reserved
4
MCP
3
XCM1
2
XCM0
1
PCM1
0
PCM0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
1
0
0
0
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CH7013A-T | Digital PC to TV Encoder |
| CH7013A-V | Digital PC to TV Encoder |
| CHB1143 | CHB1143 |
| CHF12545CBF | 500 W Power RF Flanged Chip Termination |
| CHF12545CBF500L | 500 W Power RF Flanged Chip Termination |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CH7013A-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder |
| CH7013A-V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder |
| CH7013B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder |
| CH7013B-D | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder |
| CH7013B-DF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder |
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