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Integrated Memories
MOTOROLA
ColdFire2/2M User’s Manual
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5-5
5.1.3.10 INSTRUCTION CACHE TAG OUTPUT BUS (ICHT_DO[31:8]).
signals provide the read data path between the cache tag RAM and the ColdFire2/2M. The
data bus size depends upon the size of the CACHE; see
Table 5-1
. Bit eight is always the
valid bit and is always used regardless of the cache configuration as shown in
Table 5-2
.
This bus should be connected to the data outputs (DBO) of the compiled cache tag RAM.
Unused signals must be tied low.
These input
5.1.3.11 INSTRUCTION CACHE TAG STROBE (ICHT_ST).
read or write cycle to the cache tag RAM on a low-to-high transition. This signal should be
connected to the strobe input (ST) signal of the compiled cache tag RAM.
This output signal initiates a
5.1.3.12 INSTRUCTION CACHE TAG READ/WRITE (ICHT_RWB).
indicates the direction of the data transfer to the cache tag RAM. A high level indicates a
read cycle and a low level indicates a write cycle. It should be connected to the read/write
(RWB) signal of the compiled cache tag RAM.
This output signal
5.1.4 Interaction With Other Modules
Since the instruction cache, high-speed ROM and RAM modules are connected to the
processor’s local data bus, certain user-defined configurations may result in simultaneous
instruction fetch processing. If the referenced address is mapped into the ROM or RAM
module, that module will service the request in a single cycle. In this case, data accessed
from the instruction cache is simply discarded, and no external memory references are
generated. The RAM module has higher priority over the ROM module. If the address is not
mapped into the RAM or ROM space, then the request is handled by the instruction cache
in the normal fashion.
5.1.5 Memory Reference Attributes
For every memory reference generated by the processor or the debug module, a set of
“effective attributes” is determined based on the address and the Access Control Registers
(ACR0, ACR1). This set of attributes includes the cacheable/non-cacheable definition, the
precise/imprecise handling of operand writes and the write-protect capability.
In particular, each address is compared to the values programmed in the Access Control
Registers. If the address matches one of the ACR values, the access attributes from that
Table 5-2. Valid Tag RAM Data Signals
CACHE SIZE
(BYTES)
512
1 K
2 K
4 K
8 K
16K
32K
VALID DATA BITS
CPU DATA PLACED ON
VALID DATA BITS
{MADDR[31:9], VALID}
MADDR[31:10], VALID}
MADDR[31:11], VALID}
MADDR[31:12], VALID}
MADDR[31:13], VALID}
MADDR[31:14], VALID}
MADDR[31:15], VALID}
ICHT_Dx[31:8]
ICHT_Dx[31:10,8]
ICHT_Dx[31:11,8]
ICHT_Dx[31:12,8]
ICHT_Dx[31:13,8]
ICHT_Dx[31:14,8]
ICHT_Dx[31:15,8]
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n
.