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參數(shù)資料
| 型號： | CP2105-F01-GM |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SGL USB-DL UART BRIDGE 24QFN |
| 產(chǎn)品培訓模塊： | CP21xx USB Bridge |
| 標準包裝： | 75 |
| 應用： | UART 至 USB 電橋 |
| 接口： | UART，USB |
| 電源電壓： | 1.8V，3 V ~ 3.6 V |
| 封裝/外殼： | 24-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 24-QFN（4x4） |
| 包裝： | 管件 |
| 安裝類型： | 表面貼裝 |
| 配用： | 336-2005-ND - KIT EVAL FOR CP2105 |
| 其它名稱： | 336-2009-5 |
CP2105
Rev. 1.1
15
8. GPIO Pins
The CP2105 supports five user-configurable GPIO pins for status and control information. The Standard
Communication Interface (SCI) has three GPIO pins and the Enhanced Communication Interface (ECI) has two
GPIO pins. To use the pins as GPIO pins, the interface with the GPIO pins must be configured in GPIO Mode. By
default, both communication interfaces on the CP2105 are configured for GPIO Mode. If the Modem Control
signals are needed, the interface must be configured for Modem Mode. See Section 7 for more information on
Modem Mode.
Each of these GPIO pins are usable as inputs, open-drain outputs, or push-pull outputs. Four of the GPIO pins also
have alternate functions listed in Table 12 (GPIO.2_SCI does not have an alternate function).
By default, all of the GPIO pins are configured as a GPIO input. The configuration of the pins is one-time
programmable for each device. The difference between an open-drain output and a push-pull output is when the
GPIO output is driven to logic high. A logic high, open-drain output pulls the pin to the VIO rail through an internal,
pull-up resistor. A logic high, push-pull output directly connects the pin to the VIO voltage. Open-drain outputs are
typically used when interfacing to logic at a higher voltage than the VIO pin. These pins can be safely pulled to the
higher, external voltage through an external pull-up resistor. The maximum external pull-up voltage is 5 V.
The speed of reading and writing the GPIO pins is subject to the timing of the USB bus. GPIO pins configured as
inputs or outputs are not recommended for real-time signalling.
More information regarding the configuration and usage of these pins can be found in “AN721: CP21xx Device
Customization Guide” and “AN223: Runtime GPIO Control for CP210x” available on the Silicon Labs website.
8.1. GPIO.0-1—Transmit and Receive Toggle
GPIO.0 and GPIO.1 are configurable as Transmit Toggle and Receive Toggle pins for both the Enhanced
Communication Interface and the Standard Communication Interface. These pins are logic high when a device is
not transmitting or receiving data, and they toggle at a fixed rate as specified in Table 6 when data transfer is in
progress. Typically, these pins are connected to two LEDs to indicate data transfer.
Figure 5. Transmit and Receive Toggle Typical Connection Diagram
Table 12. GPIO Mode Alternate Functions
GPIO Pin
Alternate Function
GPIO.0_ECI
TX Toggle
GPIO.1_ECI
RX Toggle/RS-485 Transceiver Control
GPIO.0_SCI
TX Toggle
GPIO.1_SCI
RX Toggle
CP2105
GPIO.0 – TX Toggle
GPIO.1 – RX Toggle
VIO
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CP2105-F01-GMR | 功能描述:輸入/輸出控制器接口集成電路 USB to Dual UART bridge RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| CP2105-F05-GMR | 制造商:Silicon Laboratories Inc 功能描述:USB TO DUAL UART BRIDGE - Tape and Reel |
| CP2105-GM | 制造商:SILABS 制造商全稱:SILABS 功能描述:Data format: 8 data bits, 1 stop bit Parity: Even, Pdd, No parity Baud rates: 2400 bps to 921600 bps |
| CP2108-B01-GM | 功能描述:輸入/輸出控制器接口集成電路 USB to QUAD UART RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray |
| CP2108-B01-GMR | 制造商:Silicon Laboratories Inc 功能描述:USB TO QUAD UART - Tape and Reel 制造商:Silicon Laboratories Inc 功能描述:IC BRIDGE USB TO UART 64QFN 制造商:Silicon Laboratories Inc 功能描述:USB to QUAD UART |
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