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參數(shù)資料
| 型號(hào)： | CP82C50A-5Z |
| 廠商： | Intersil |
| 文件頁數(shù)： | 1/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ASYNC COMM ELEMENT UART 40DIP |
| 標(biāo)準(zhǔn)包裝： | 9 |
| 特點(diǎn)： | 單芯片 UART/BRG |
| 通道數(shù)： | 1，UART |
| 規(guī)程： | RS232C |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 帶并行端口： | 是 |
| 帶故障啟動(dòng)位檢測(cè)功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 40-DIP（0.600"，15.24mm） |
| 供應(yīng)商設(shè)備封裝： | 40-DIP |
| 包裝： | 管件 |
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2003, 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
CMOS Asynchronous
The 82C50A Asynchronous Communication Element
(ACE) is a high performance programmable Universal
Asynchronous Receiver/Transmitter (UART) and Baud
Rate Generator (BRG) on a single chip. Using Intersil’s
advanced Scaled SAJI IV CMOS Process, the ACE will
support data rates from DC to 625K baud (0-10MHz clock).
The ACE’s receiver circuitry converts start, data, stop, and
parity bits into a parallel data word. The transmitter circuitry
converts a parallel data word into serial form and appends
the start, parity, and stop bits. The word length is
programmable to 5, 6, 7, or 8 data bits. Stop bit selection
provides a choice of 1,1.5, or 2 stop bits.
The Baud Rate Generator divides the clock by a divisor
programmable from 1 to 216-1 to provide standard RS-
232C baud rates when using any one of three industry
standard baud rate crystals (1.8432MHz, 2.4576MHz, or
3.072MHz). A programmable buffered clock output
(BAUDOUT) provides either a buffered oscillator or 16X (16
times the data rate) baud rate clock for general purpose
system use.
To meet the system requirements of a CPU interfacing to
an asynchronous channel, the modem control signals RTS,
CTS, DSR, DTR, RI, DCD are provided. Inputs and outputs
have been designed with full TTL/CMOS compatibility in
order to facilitate mixed TTL/NMOS/CMOS system design.
Features
Single Chip UART/BRG
DC to 625K Baud (DC to 10MHz Clock)
Crystal or External Clock Input
On Chip Baud Rate Generator 1 to 65535 Divisor
Generates 16X Clock
Prioritized Interrupt Mode
Fully TTL/CMOS Compatible
Microprocessor Bus Oriented Interface
80C86/80C88 Compatible
Scaled SAJI IV CMOS Process
Low Power - 1mA/MHz Typical
Modem Interface
Line Break Generation and Detection
Loopback and Echo Modes
Doubled Buffered Transmitter and Receiver
Single 5V Supply
Pb-Free Plus Anneal Available (RoHS Compliant)
Ordering Information
625K BAUD
PART
MARKING
TEMP
RANGE
(°C)
PACKAGE
PKG.
DWG. #
CP82C50A-5
0 to +70
40 Ld PDIP
E40.6
CP82C50A-5Z
(Note)
CP82C50A-5Z
0 to +70
40 Ld PDIP
(Pb-free)
E40.6
CS82C50A-596
CS82C50A-5
0 to +70
44 Ld PLCC
Tape and
Reel
N44.65
CS82C50A-5Z
(Note)
CS82C50A-5Z
0 to +70
44 Ld PLCC
(Pb-free)
N44.65
CS82C50A-5Z96
(Note)
CS82C50A-5Z
0 to +70
44 Ld PLCC
Tape and
Reel
(Pb-free)
N44.65
IS82C50A-5
-40 to +85 44 Ld PLCC N44.65
IS82C50A-5Z
(Note)
IS82C50A-5Z
-40 to +85 44 Ld PLCC
(Pb-free)
N44.65
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN2958.5
82C50A
Data Sheet
August 24, 2006
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