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參數(shù)資料
| 型號： | CP82C59A-12Z |
| 廠商： | Intersil |
| 文件頁數(shù)： | 18/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PERIPH INTERRUPT CTRLR 28-DIP |
| 標(biāo)準(zhǔn)包裝： | 143 |
| 控制器類型： | CMOS 優(yōu)先中斷控制器 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 電流 - 電源： | 1mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 28-DIP（0.600"，15.24mm） |
| 供應(yīng)商設(shè)備封裝： | 28-PDIP |
| 包裝： | 管件 |
5
FN2784.5
March 17, 2006
A more desirable method would be one that would allow the
microprocessor to be executing its main program and only
stop to service peripheral devices when it is told to do so by
the device itself. In effect, the method would provide an
external asynchronous input that would inform the processor
that it should complete whatever instruction that is currently
being executed and fetch a new routine that will service the
requesting device. Once this servicing is complete, however,
the processor would resume exactly where it left off.
This is the Interrupt-driven method. It is easy to see that
system throughput would drastically increase, and thus,
more tasks could be assumed by the microcomputer to
further enhance its cost effectiveness.
The Programmable Interrupt Controller (PlC) functions as an
overall manager in an Interrupt-Driven system. It accepts
requests from the peripheral equipment, determines which of
the incoming requests is of the highest importance (priority),
ascertains whether the incoming request has a higher
priority value than the level currently being serviced, and
issues an interrupt to the CPU based on this determination.
Each peripheral device or structure usually has a special
program or “routine” that is associated with its specific
functional or operational requirements; this is referred to as a
“service routine”. The PlC, after issuing an interrupt to the
CPU, must somehow input information into the CPU that can
“point” the Program Counter to the service routine
associated with the requesting device. This “pointer” is an
address in a vectoring table and will often be referred to, in
this document, as vectoring data.
82C59A Functional Description
The 82C59A is a device specifically designed for use in real
time, interrupt driven microcomputer systems. It manages
eight levels of requests and has built-in features for
expandability to other 82C59As (up to 64 levels). It is
programmed by system software as an I/O peripheral. A
selection of priority modes is available to the programmer so
that the manner in which the requests are processed by the
82C59A can be configured to match system requirements.
The priority modes can be changed or reconfigured
dynamically at any time during main program operation. This
means that the complete interrupt structure can be defined
as required, based on the total system environment.
ROM
I/O (2)
RAM
CPU
INT
I/O (1)
I/O (N)
PIC
FIGURE 3. INTERRUPT METHOD
IR0
IR1
IR2
CASCADE
BUFFER
COMPARATOR
READ/
WRITE
LOGIC
DATA
BUS
BUFFER
IN
SERVICE
REG
(ISR)
PRIORITY
RESOLVER
INTERRUPT MASK REG
(IMR)
INTERRUPT
REQUEST
REG
(IRR)
CONTROL LOGIC
INT
INTA
IR3
IR4
IR5
IR6
IR7
CAS 0
CAS 1
CAS 2
RD
WR
A0
SP
/EN
CS
D7 - D0
INTERNAL BUS
FIGURE 4. 82C59A FUNCTIONAL DIAGRAM
82C59A
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