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參數(shù)資料
| 型號： | CP82C59A-12Z |
| 廠商： | Intersil |
| 文件頁數(shù)： | 8/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PERIPH INTERRUPT CTRLR 28-DIP |
| 標(biāo)準(zhǔn)包裝： | 143 |
| 控制器類型： | CMOS 優(yōu)先中斷控制器 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 電流 - 電源： | 1mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 28-DIP（0.600"，15.24mm） |
| 供應(yīng)商設(shè)備封裝： | 28-PDIP |
| 包裝： | 管件 |
16
FN2784.5
March 17, 2006
The Special Fully Nested Mode
This mode will be used in the case of a big system where
cascading is used, and the priority has to be conserved
within each slave. In this case the special fully nested mode
will be programmed to the master (using lCW4). This mode
is similar to the normal nested mode with the following
exceptions:
a. When an interrupt request from a certain slave is in ser-
vice, this slave is not locked out from the master’s priority
logic and further interrupt requests from higher priority
IRs within the slave will be recognized by the master and
will initiate interrupts to the processor. (In the normal
nested mode a slave is masked out when its request is in
service and no higher requests from the same slave can
be serviced.
b. When exiting the Interrupt Service routine the software
has to check whether the interrupt serviced was the only
one from that slave. This is done by sending a non-spe-
cific End of Interrupt (EOI) command to the slave and
then reading its In-Service register and checking for zero.
If it is empty, a non-specified EOI can be sent to the mas-
ter, too. If not, no EOI should be sent.
Buffered Mode
When the 82C59A is used in a large system where bus
driving buffers are required on the data bus and the
cascading mode is used, there exists the problem of
enabling buffers
The buffered mode will structure the 82C59A to send an
enable signal on SP/EN to enable the buffers. In this mode,
whenever the 82C59A’s data bus outputs are enabled, the
SP/EN output becomes active.
This modification forces the use of software programming to
determine whether the 82C59A is a master or a slave. Bit 3
in ICW4 programs the buffered mode, and bit 2 in lCW4
determines whether it is a master or a slave.
Cascade Mode
The 82C59A can be easily interconnected in a system of one
master with up to eight slaves to handle up to 64 priority
levels.
The master controls the slaves through the 3 line cascade
bus (CAS2 - 0). The cascade bus acts like chip selects to the
slaves during the INTA sequence.
In a cascade configuration, the slave interrupt outputs (INT)
are connected to the master interrupt request inputs. When a
slave request line is activated and afterwards acknowledged,
the master will enable the corresponding slave to release the
device routine address during bytes 2 and 3 of INTA. (Byte 2
only for 80C86/88/286).
The cascade bus lines are normally low and will contain the
slave address code from the leading edge of the first INTA
pulse to the trailing edge of the last INTA pulse. Each
82C59A in the system must follow a separate initialization
sequence and can be programmed to work in a different
mode. An EOI command must be issued twice: once for the
master and once for the corresponding slave. Chip select
decoding is required to activate each 82C59A.
NOTE: Auto EOI is supported in the slave mode for the 82C59A.
The cascade lines of the Master 82C59A are activated only
for slave inputs, non-slave inputs leave the cascade line
inactive (low). Therefore, it is necessary to use a slave
address of 0 (zero) only after all other addresses are used.
FIGURE 11. CASCADING THE 82C59A
CS
82C59A
SLAVE A
CAS 0
CAS 1
CAS 2
INT
A0 D7 - D0 INTA
SP
/EN 75
6
4 3 210
GND
75
6
4 3 210
CS
82C59A
SLAVE B
CAS 0
CAS 1
CAS 2
INT
A0 D7 - D0 INTA
SP
/EN 75
6
432 10
GND
75
6
432 10
CS
MASTER 82C59A
CAS 0
CAS 1
CAS 2
INT
A0 D7 - D0 INTA
SP
/EN 75
6
4 3210
VCC
75 42 1 0
3
6
INT REQ
DATA BUS (8)
CONTROL BUS
ADDRESS BUS (16)
INTERRUPT REQUESTS
82C59A
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