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參數(shù)資料
| 型號(hào)： | CPC7514Z |
| 廠商： | IXYS Integrated Circuits Division |
| 文件頁(yè)數(shù)： | 3/15頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC LINE CARD ACCESS SWITC 20SOIC |
| 標(biāo)準(zhǔn)包裝： | 38 |
| 功能： | 線路卡接入交換 |
| 接口： | TTL |
| 電路數(shù)： | 2 |
| 電源電壓： | 3 V ~ 3.6 V |
| 電流 - 電源： | 4.5mA |
| 工作溫度： | -40°C ~ 110°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SOIC |
| 包裝： | 管件 |
| 包括： | 免彈跳切換，第三級(jí)保護(hù) |
| 其它名稱： | CLA379 |
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INTEGRATED CIRCUITS DIVISION
CPC7514
R06
www.ixysic.com
11
be reconfigured by setting the LATCHx input low. Prior
to the assertion of a logic low at the LATCHx pin, the
switch control inputs must be properly conditioned.
3.3.1 Data Latch
The CPC7514 has two integrated transparent data
latches. The latch-enable operation is controlled by
logic input levels at the LATCHx pins. Data input to the
latch is via the INx input pins while the outputs of the
data latch are internal nodes used for state control.
When the latch enable control pin is at a logic 0 the
data latch is transparent and the input control signals
flow directly through the data latch to the state control
circuitry. A change in input will be reflected by a
change in the switch state.
Whenever the latch enable control pin is at logic 1, the
data latch is active and the control data is locked.
Subsequent changes to the INx input control pins will
not result in a change to the control logic or affect the
existing switch states.
The switches will remain in the state they were in
when the LATCHx changes from logic 0 to logic 1, and
will not respond to changes in input as long as the
LATCHx is at logic 1. However, the TSDx are not
affected by the latch function. Since internal thermal
shutdown control is not affected by the state of the
latch enable input, TSDx will override state control.
3.3.2 TPin Description
The TSDx pins are bidirectional I/O structures with
internal pull-up resistors sourced from VDD. As
outputs, these pins indicate the status of the thermal
shutdown circuitry for the associated channel.
Typically, during normal operation, these pins will be
pulled up to VDD, but, under fault conditions that create
excess thermal loading, the channel under duress will
enter thermal shutdown and a logic low will be output
at TSDx.
As inputs, the TSDx pins are utilized to place the
channel into the All-Off state by simply pulling the
input low. This is a convenient way to temporarily
place the channel’s switches into the off state without
the need to cycle the inputs and LATCH through an off
and then an on sequence.
For applications using logic devices powered from a
supply voltage that differs from the CPC7514, (lower
or higher than VDD), IXYS Integrated Circuits Division
recommends the use of an open-collector or an
open-drain type output to control TSDx. For
lower-voltage logic control, this avoids sinking the
TSDx pull-up bias current to ground during normal
operation when the All-Off state is not required. And
for higher logic-voltage control, this prevents
over-voltage biasing of the TSDx input.
If TSDx is forced to a logic 1 or tied to VDD, the channel
just ignores this input, and still enters the thermal
shutdown state at high temperature. In other words,
the thermal shutdown feature can not be overridden
by an external pull-up on the TSDx control.
3.4 Power Supplies
Only a +3.3V logic supply and ground are connected
to the CPC7514. Switch state control is powered
exclusively by the +3.3V supply. As a result, the
CPC7514 exhibits extremely low power consumption
during active and idle states.
3.5 Protection
The CPC7514 provides protection for both the low
voltage side circuitry it connects to high voltage
networks and itself. Three separate layers of
protection are interleaved within the device to protect
against high-energy high-frequency transients and
high-power, low-frequency fault conditions.
3.5.1 Dynamic High Frequency Current Limit
High voltage networks are ofttimes located in
environments susceptible to lightning events resulting
in high-frequency, high-energy transients being
coupled onto the high voltage network. Low voltage
circuits accessing high voltage networks through the
CPC7514 are protected from these events by the
dynamic high-frequency current-limit response
incorporated into each switch.
While in the ON state, the high frequency current is
restricted by the CPC7514. For a GR-1089-CORE
specified +1000V 10x1000
s lightning pulse with a
generator source impedance of 10
applied to the
high voltage network though a properly clamped
external protector, the current seen at the CPC7514
low voltage side interface will be a pulse with a typical
magnitude of 1A and a duration less than 0.5
s.
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