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參數(shù)資料
| 型號： | CS2200P-DZZR |
| 廠商： | CIRRUS LOGIC INC |
| 元件分類： | PLL合成/DDS/VCOs |
| 中文描述： | PHASE LOCKED LOOP, 56 MHz, PDSO10 |
| 封裝： | 3 MM, LEAD FREE, MO-187, MSOP-10 |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 177K |
| 代理商： | CS2200P-DZZR |
CS2200-OTP
DS842F2
19
6.3.3
Enable PLL Clock Output on Unlock (ClkOutUnl)
Defines the state of the PLL output during the PLL unlock condition.
6.3.4
M2 Pin Configuration (M2Config[2:0])
Controls which special function is mapped to the M2 pin
.
ClkOutUnl
Clock Output Enable Status
0
Clock outputs are driven ‘low’ when PLL is unlocked.
1
Clock outputs are always enabled (results in unpredictable output when PLL is unlocked).
Application:
“PLL Clock Output” on page 13
M2Config[2:0]
M2 pin function
000
Disable CLK_OUT pin.
001
Disable AUX_OUT pin.
010
Disable CLK_OUT and AUX_OUT.
011
RModSel[1:0] Modal Parameter Enable.
100
Reserved.
101
Reserved.
110
Reserved.
111
Force AuxOutSrc[1:0] = 10 (PLL Clock Out).
Application:
“M2 Mode Pin Functionality” on page 15
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