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參數(shù)資料
| 型號： | CS4192XDWFR16G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 3/8頁 |
| 文件大小： | 0K |
| 描述： | IC DRIVER AIR CORE SINGLE 16SOIC |
| 產(chǎn)品變化通告： | Product Discontinuation 09/Jan/2008 |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 驅(qū)動器 |
| 驅(qū)動器/接收器數(shù)： | 1/0 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC W |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | CS4192XDWFR16GOS |
CS4192
http://onsemi.com
3
ELECTRICAL CHARACTERISTICS (40
Characteristic
Test Conditions
Min
Typ
Max
Unit
Supply Voltages and Currents
VBB Quiescent Current
Output disabled (OE = 0 V)
[RCOS, RSIN = RL(MIN)] @ 45°
(code = X’080) VBB = 14 V
1.0
5.0
175
mA
VCC Quiescent Current
OE, CS, DI = high, VBB = 0 V, SCLK = 2.0 MHz
1.15
mA
Digital Inputs and Outputs
Output High Voltage
SO, IOH = 0.8 mA
VCC 0.8
V
Output Low Voltage
SO, IOL = 0.8 mA
ST, IOL = 2.5 mA
0.4
0.8
V
Output Off Leakage
ST, VCC = 5.0 V
25
mA
Input High Voltage
0.7
× VCC
V
Input Low Voltage
CS, SCLK, SI, OE
0.3
× VCC
V
Input High Current
CS, SCLK, SI, OE; VIN = 0.7 × VCC
1.0
mA
Input Low Current
CS, SCLK, SI, OE; VIN = 0.3 × VCC
1.0
mA
Analog Outputs
Output Function Accuracy
1.2
±0.5
+1.2
deg
Output Shutdown Current, Source
VBB = 14 V
70
125
250
mA
Output Shutdown Current, Sink
VBB = 14 V
70
125
250
m
Α
Output Shutdown Current, Source
VBB = 7.5 V
43
125
250
m
Α
Output Shutdown Current, Sink
VBB = 7.5 V
43
125
250
m
Α
Thermal Shutdown
170
°C
Thermal Shutdown Hysteresis
20
°C
Coil Drive Output Voltage
0.748
×
VBB
V
Minimum Load Resistance
TA = 105°C
TA = 25°C
TA = 40°C
229
171
150
W
Shift Clock Frequency
2.0
MHz
SCLK High Time
175
ns
SCLK Low Time
175
ns
SO Rise Time
0.75 V to VCC 1.2 V; CL = 90 pF
150
ns
SO Fall Time
0.75 V to VCC 1.2 V; CL = 90 pF
150
ns
SO Delay Time
CL = 90 pF
150
ns
SI Setup Time
75
ns
SI Hold Time
75
ns
CS Setup Time
Note 3.
0
ns
CS Hold Time
75
ns
2. Designed to meet these characteristics over the stated voltage and temperature ranges, though may not be 100% parametrically tested in
production.
3. OE must be high at falling edge of CS. This condition ensures valid output for any given input.
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