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參數(shù)資料
| 型號(hào)： | CS4192XDWFR16G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DRIVER AIR CORE SINGLE 16SOIC |
| 產(chǎn)品變化通告： | Product Discontinuation 09/Jan/2008 |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 驅(qū)動(dòng)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 1/0 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC W |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | CS4192XDWFR16GOS |
CS4192
http://onsemi.com
6
II
I
III
IV
270
°
VSIN
VSIN+
90
°
VCOS
VCOS+
180
°
360/0
°
0.748 VBB
q
Figure 3. Gauge Response
To drive the gauge’s pointer to a particular angle, the
microcontroller sends a 10bit digital word into the serial
port. These 10 bits are divided as shown in Figure 4.
Gauge
(360
°)
MSB
LSB
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D9D7 select
which octant
Divides a 45
° octant into 128 equal parts to
achieve a 0.35
° resolution Code 012710
Figure 4. Definition of Serial Word
However, from a software programmers viewpoint, a
360
° circle is divided into 1024 equal parts of 0.35° each.
Table 1 shows the data associated with the 45
° divisions of
the 360
° driver.
Table1. Nominal Output (VBB = 14 V)
Input Code
(Decimal)
Ideal
Degrees
Nominal
Degrees
VSIN
(V)
VCOS
(V)
0
0.176
0.032
10.476
128
45
45.176
10.476
10.412
256
90
90.176
10.476
0.032
384
135
135.176
10.412
10.476
512
180
180.176
0.032
10.476
640
225
225.176
10.476
10.412
768
270
270.176
10.476
0.032
896
315
315.176
10.476
1023
359.65
359.826
0.032
10.476
The 10 bits are shifted into the device’s shift register MSB
first using an SPI compatible scheme. This method is shown
in Figure 5. The CS must be high and remain high for SCLK
to be enabled. Data on SI is shifted in on the rising edge of
the synchronous clock signal. Data in the shift register
changes at SO on the falling edge of SCLK. This
arrangement allows the cascading of devices. SO is always
enabled. Data shifts through without affecting the outputs
until CS is brought low. At this time the internal DAC is
updated and the outputs change accordingly.
CS
SI
SCLK
SO
SI(Setup)
SI(Hold)
SI(tpd)
SO(Rise, Fall)
10% 90%
CSHold
CSSetup
Figure 5. Serial Data Timing Diagram
Figure 6 shows the powerup sequence for the CS4192.
Note the IC requires a pulse on the Chip Select (CS) pin to
clear the Status Fault (ST) after power up. OE must be high
before the falling edge of CS to enable the output buffers.
VCC
CS
SI
OE
ST
10
Bits
10
Bits
OUTPUTS
ENABLED
Registers
set
to
zero
Registers
set
to
zero
OUTPUTS
ENABLED
Figure 6. Power Up Sequence
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