參數(shù)資料
型號(hào): CS4265-DNZR
廠商: Cirrus Logic Inc
文件頁(yè)數(shù): 35/46頁(yè)
文件大?。?/td> 0K
描述: IC CODEC 24BIT 104DB 32-QFN
標(biāo)準(zhǔn)包裝: 6,000
類型: 立體聲音頻
數(shù)據(jù)接口: 串行
分辨率(位): 24 b
ADC / DAC 數(shù)量: 2 / 2
三角積分調(diào)變:
動(dòng)態(tài)范圍,標(biāo)準(zhǔn) ADC / DAC (db): 104 / 104
電壓 - 電源,模擬: 3.13 V ~ 5.25 V
電壓 - 電源,數(shù)字: 3.13 V ~ 5.25 V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 32-QFN
供應(yīng)商設(shè)備封裝: 32-QFN 裸露焊盤(pán)(5x5)
包裝: 帶卷 (TR)
配用: 598-1001-ND - BOARD EVAL FOR CS4265 CODEC
40
DS657F3
CS4265
6.6
Signal Selection - Address 06h
6.6.1
DAC SDIN Source (Bit 7)
Function:
This bit is used to select the serial audio data source for the DAC as shown in Table 12.
6.6.2
Digital Loopback (Bit 1)
Function:
When this bit is set, an internal digital loopback from the ADC to the DAC will be enabled. Please refer to
6.7
Channel B PGA Control - Address 07h
6.7.1
Channel B PGA Gain (Bits 5:0)
Function:
6.8
Channel A PGA Control - Address 08h
6.8.1
Channel A PGA Gain (Bits 5:0)
Function:
Sets the gain or attenuation for the ADC input PGA stage. The gain may be adjusted from -12 dB to
+12 dB in 0.5 dB steps. The gain bits are in two’s complement with the Gain0 bit set for a 0.5 dB step.
Register settings outside of the ±12 dB range are reserved and must not be used. See Table 13 for ex-
ample settings.
76
543
21
0
SDINSel
Reserved
LOOP
Reserved
SDINSel Setting
DAC Data Source
0
SDIN1
1
SDIN2
Table 12. DAC SDIN Source Selection
76
543
21
0
Reserved
Gain5
Gain4
Gain3
Gain2
Gain1
Gain0
76
543
21
0
Reserved
Gain5
Gain4
Gain3
Gain2
Gain1
Gain0
Gain[5:0]
Setting
101000
-12 dB
000000
0 dB
011000
+12 dB
Table 13. Example Gain and Attenuation Settings
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