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參數(shù)資料
| 型號： | CS4334-KSZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 7/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC STER 24BIT 96KHZ 8-SOIC |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 104mW |
| 工作溫度： | -10°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電壓，單極 |
| 采樣率（每秒）： | 96k |
| 產(chǎn)品目錄頁面： | 756 (CN2011-ZH PDF) |
| 配用： | 598-1510-ND - BOARD EVAL FOR CS4334 CODEC |
| 其它名稱： | 598-1046-5 |
15
CS4334/5/8/9
down state is related to the value of the DC-blocking capacitance. For example, with a 3.3
F capacitor, the
time that the device must remain in the power-down state will be approximately 0.4 seconds.
4.6
Grounding and Power Supply Decoupling
As with any high resolution converter, the CS4334 family requires careful attention to power supply and
grounding arrangements to optimize performance. Figure 1 shows the recommended power arrangement
with VA connected to a clean +5V supply. For best performance, decoupling capacitors should be located
as close to the device package as possible with the smallest capacitor closest.
4.7
Analog Output and Filtering
The analog filter present in the CS4334 family is a switched-capacitor filter followed by a continuous time
low pass filter. Its response, combined with that of the digital interpolator, is given in Figures 15 - 22.
LRCK
SCLK
Left Channel
Right Channel
SDATA
+3 +2 +1 LSB
+5 +4
MSB -1 -2 -3 -4 -5
+3 +2 +1 LSB
+5 +4
MSB -1 -2 -3 -4
Internal SCLK Mode
External SCLK Mode
IS, 16-Bit data and INT SCLK = 32 Fs if
MCLK/LRCK = 512, 256 or 128
IS, Up to 24-Bit data and INT SCLK = 48 Fs if
MCLK/LRCK = 384 or 192
IS, up to 24-Bit Data
Data Valid on Rising Edge of SCLK
Figure 10. CS4334 Data Format (IS)
LRCK
SCLK
Left Channel
Right Channel
SDATA
+3 +2 +1 LSB
+5 +4
MSB -1 -2 -3 -4 -5
+3 +2 +1 LSB
+5 +4
MSB -1 -2 -3 -4
Internal SCLK Mode
External SCLK Mode
Left Justified, up to 24-Bit Data
INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128
INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
Left Justified, up to 24-Bit Data
Data Valid on Rising Edge of SCLK
Figure 11. CS4335 Data Format
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS4334-KSZR | 功能描述:數(shù)模轉(zhuǎn)換器- DAC IC 8-Pin 24Bit 96kHz Stereo DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| CS4335 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:8-Pin, 24-Bit, 96 kHz Stereo D/A Converter |
| CS4335-BS | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:8-Pin, 24-Bit, 96 kHz Stereo D/A Converter |
| CS4335-DS | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:8-Pin, 24-Bit, 96 kHz Stereo D/A Converter |
| CS4335-DSZ | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:8-Pin, 24-Bit, 96 kHz Stereo D/A Converter |
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