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參數(shù)資料
| 型號(hào)： | CS4382A-CQZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 19/50頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 8CH 114DB 192KHZ 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 位數(shù)： | 24 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 8 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 680mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 16 電壓，單極 |
| 采樣率（每秒）： | 192k |
| 配用： | 598-1524-ND - BOARD EVAL FOR CS4382A DAC |
| 其它名稱： | 598-1061 |
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26
DS618F2
CS4382A
4.8
Direct Stream Digital (DSD) Mode
In Stand-alone Mode, DSD operation is selected by holding DSD_EN(LRCK) high and applying the DSD
data and clocks to the appropriate pins. The M[2:0] pins set the expected DSD rate and MCLK ratio.
In Control Port Mode, the FM bits set the device into DSD Mode (DSD_EN pin is not required to be held
high). The DIF register then controls the expected DSD rate and MCLK ratio.
During DSD operation, the PCM related pins should either be tied low or remain active with clocks (except
LRCK in Stand-alone Mode). When the DSD related pins are not being used, they should either be tied static
low or remain active with clocks (except M3 in Stand-alone Mode).
4.9
Grounding and Power Supply Arrangements
As with any high-resolution converter, the CS4382A requires careful attention to power supply and ground-
ing arrangements if its potential performance is to be realized. The Typical Connection Diagram shows the
recommended power arrangements, with VA, VD, VLC, and VLS connected to clean supplies. If the ground
planes are split between digital ground and analog ground, the GND pins of the CS4382A should be con-
nected to the analog ground plane.
All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted
coupling into the DAC.
4.9.1
Capacitor Placement
Decoupling capacitors should be placed as close to the DAC as possible, with the low-value ceramic ca-
pacitor being the closest. To further minimize impedance, these capacitors should be located on the same
layer as the DAC. If desired, all supply pins with similar voltage ratings may be connected to the same
supply, but a decoupling capacitor should still be placed on each supply pin.
Notes:
All decoupling capacitors should be referenced to analog ground.
The CDB4382A evaluation board demonstrates the optimum layout and power supply arrangements.
4.10
Analog Output and Filtering
The application note “Design Notes for a 2-pole Filter with Differential Input” discusses the second-order
Butterworth filter and differential-to-single-ended converter which was implemented on the CS4382A eval-
pensation for an external filter. Therefore, the DAC system phase and amplitude response will be dependent
on the external analog circuitry. The off-chip filter has been designed to attenuate the typical full-scale out-
put level to below 2 Vrms.
Figure 15 shows how the full-scale differential analog output level specification is derived.
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|---|---|
| CS4382A-CQZR | 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC IC 114dB 192 kHz 8Ch DAC w/DSD supt RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
| CS4382A-DQZ | 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC 8-Ch DAC 24-Bit 192kHz 114dB w/DSD RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
| CS4382A-DQZR | 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC IC 114dB 192 kHz 8Chn DAC w/DSD supt. RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel |
| CS4382A-EQZ | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:114 dB, 192 kHz 8-channel D/A Converter |
| CS4382A-EQZR | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:114 dB, 192 kHz 8-channel D/A Converter |
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