參數(shù)資料
型號(hào): CS47028C-CQZ
廠商: CIRRUS LOGIC INC
元件分類: 數(shù)字信號(hào)處理
中文描述: 0-BIT, 24.576 MHz, OTHER DSP, QFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026, LQFP-100
文件頁數(shù): 5/17頁
文件大?。?/td> 479K
代理商: CS47028C-CQZ
CS470xx Data Sheet
Audio SOC Processor Family
DS787PP5
Copyright 2011 Cirrus Logic
13
4.3 On-chip DSP Peripherals
4.3.1 Analog to Digital Converter Port (ADC)
The ADCs in the CS470xx devices feature dynamic range performance in excess of 100 dB.
Please see Section 5.16 “ADC Characteristics” on page 27 for more details on CS470xx ADC
performance. The CS47024 and CS47028 devices support up to 2 simultaneous channels of
analog-to-digital conversion with the input source selectable using an integrated 5:1 stereo analog
mux (analog inputs AIN_2A/B through AIN_6A/B). The CS47048 device adds a second pair of
ADCs that are directly connected to input pins AIN_1A/B providing a total of 4 simultaneous
channels of analog-to-digital conversion. This feature gives the CS47048 the ability to select from a
total of six stereo pairs of analog input. A single programmable bit selects single-ended or
differential mode signals for all inputs. The conversions are performed with either Fs=96 kHz or
Fs=192 kHz.
4.3.2 Digital to Analog Converter Port (DAC)
The DACs in the CS470xx devices feature dynamic range performance in excess of 100 dB.
Please see Section 5.17 “DAC Characteristics” on page 30 for more details on CS470xx DAC
performance. The CS47024 device supports four simultaneous channels of digital-to-analog
conversion. The CS47028 and CS47048 devices provide eight simultaneous channels of digital-to-
analog conversion. The DACs have voltage mode outputs that can be connected either as single-
ended or differential signals. The conversions are performed with Fs=96 kHz.
4.3.3 Digital Audio Input Port (DAI)
The input capabilities for each version of the CS470xx are summarized in Table 2 and Table 3.
Up to five DAI ports are available. Two of the DAI ports can be programmed to implement other
functions. If the SPI mode is used, the DAI_DATA4 pin becomes the SCP_CS input. The integrated
S/PDIF receiver can be used to takes over the DAI_DATA3 pin.
The DAI port PCM inputs have a single slave-only clock domain. The S/PDIF receiver, if used, is a
separate clock domain. The output of the S/PDIF Rx can then be converted through one of the
internal SRC blocks to synchronize with the PCM input. The sample rate of the input clock domains
can be determined automatically by the DSP, off-loading the task of monitoring the S/PDIF Rx from
the host. A time-stamping feature provides the ability to also sample-rate convert the input data via
software.The DAI port supports PCM format with word lengths up to 32 bits and sample rates as
high as 192 kHz.
The DAI also supports a time division multiplexed (TDM) mode that packs up to 10 PCM audio
channels on a single data line.
4.3.4 S/PDIF RX Input Port (DAI)
One of the PCM pins of the DAI can also be used as a DC-coupled, TTL-level S/PDIF Rx input
capable of receiving and demodulating bi-phase encoded S/PDIF signals with Fs
192 kHz.
4.3.5 Digital Audio Output Port (DAO)
DAO port supports PCM resolutions of up to 32-bits. The port supports sample rates (Fs) as high
as 192 kHz. The port can be configured as an independent clock domain mastered by the DSP, or
as a clock slave if an external MCLK or SCLK/LRCLK source is available.
The DAO also supports a time division multiplexed (TDM) mode, that packs up to 8 channels of
PCM audio on a single data line.
4.3.6 S/PDIF TX Output Port (DAO)
Two of the serial audio pins can be re-configured as S/PDIF TX pins that drive a bi-phase encoded
S/PDIF signal (data with embedded clock on a single line).
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