參數(shù)資料
型號(hào): CS495314-CVZ
廠商: CIRRUS LOGIC INC
元件分類: 顏色信號(hào)轉(zhuǎn)換
中文描述: COLOR SIGNAL DECODER, PQFP128
封裝: LEAD FREE, LQFP-128
文件頁(yè)數(shù): 5/35頁(yè)
文件大?。?/td> 295K
代理商: CS495314-CVZ
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
DS705PP8
13
5.9 Switching Characteristics — Internal Clock
5.10 Switching Characteristics — Serial Control Port - SPI Slave Mode
Parameter
Symbol
Min
Max
Unit
Internal DCLK frequency1
1. After initial power-on reset, Fdclk = Fxtal. After initial kick-start commands, the PLL is locked to max Fdclk and remains
locked until the next power-on reset.
Fdclk
——
MHz
CS49530x-CVZ
CS49531x-CQZ
CS49531x-CVZ
CS49530x-DVZ
CS49531x-DVZ
—Fxtal
Fxtal
150
TBD
Internal DCLK period1
DCLKP
ns
CS49530x-CVZ
CS49531x-CQZ
CS49531x-CVZ
CS49530x-DVZ
CS49531x-DVZ
—6.7
6.7
TBD
1/Fxtal
Parameter
Symbol
Min
Typical
Max
Units
SCP_CLK frequency1
1. The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that
the actual maximum speed of the communication port may be limited by the firmware application. Flow control using
the SCP_BSY pin should be implemented to prevent overflow of the input data buffer. At boot the maximum speed
is Fxtal/3.
fspisck
——
25
MHz
SCP_CS falling to SCP_CLK rising
tspicss
24
ns
SCP_CLK low time
tspickl
20
ns
SCP_CLK high time
tspickh
20
ns
Setup time SCP_MOSI input
tspidsu
5—
ns
Hold time SCP_MOSI input
tspidh
5—
ns
SCP_CLK low to SCP_MISO output valid
tspidov
——
11
ns
SCP_CLK falling to SCP_IRQ rising
tspiirqh
20
ns
SCP_CS rising to SCP_IRQ falling
tspiirql
0—
ns
SCP_CLK low to SCP_CS rising
tspicsh
24
ns
SCP_CS rising to SCP_MISO output high-Z
tspicsdz
—20
ns
SCP_CLK rising to SCP_BSY falling
tspicbsyl
—3*DCLKP+20
ns
相關(guān)PDF資料
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