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參數(shù)資料
| 型號： | CS495314-DVZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 17/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP DECODER 32BIT 128-LQFP |
| 標準包裝： | 72 |
| 系列： | * |
| 其它名稱： | 598-1944 |
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
DS705F2
7
4 Hardware Functional Description
4.1 Coyote 32-bit DSP Core
The CS4953xx is a dual-core DSP with separate X and Y data and P code memory spaces. Each core is a
high-performance, 32-bit, user-programmable, fixed-point DSP that is capable of performing two multiply
accumulate (MAC) operations per clock cycle. Each core has eight 72-bit accumulators, four X- and four Y-data
registers, and 12 index registers.
Both DSP cores are coupled to a flexible DMA engine. The DMA engine can move data between peripherals
such as the digital audio input (DAI) and digital audio output (DAO), external memory, or any DSP core
memory, all without the intervention of the DSP. The DMA engine offloads data move instructions from the DSP
core, leaving more MIPS available for signal processing instructions.
CS4953xx functionality is controlled by application codes that are stored in on-board ROM or downloaded to
the CS4953xx from a host MCU or external FLASH/EEPROM. Users can choose to use standard audio
decoder and post-processor modules which are available from Cirrus Logic.
The CS4953xx is suitable for audio decoder, audio post-processor, audio encoder, DVD audio/video player,
and digital broadcast decoder applications.
4.1.1 DSP Memory
Each DSP core has its own on-chip data and program RAM and ROM and does not require external memory
for any of today’s popular audio algorithms including Dolby Digital Surround EX, AAC Multichannel, DTS-ES
96/24, and THX Ultra2.
The memory maps for the DSPs are as follows. All memory sizes are composed of 32-bit words.
4.1.2 DMA Controller
The powerful 12-channel DMA controller can move data between eight on-chip resources. Each resource has
its own arbiter: X, Y, and P RAM/ROMs on DSP A; X, Y, and P RAM/ROMs on DSP B; external memory; and
the peripheral bus. Modulo and linear addressing modes are supported, with flexible start address and
increment controls. The service interval for each DMA channel as well as up to six interrupt events, is
programmable.
Table 3. CS49530x DSP Memory Sizes
Memory
Type
DSP A
DSP B
X
16K SRAM, 16K ROM
10K SRAM, 8K ROM
Y
16K SRAM, 32K ROM
16K SRAM, 16K ROM
P
8K SRAM, 32K ROM
8K SRAM, 24K ROM
Table 4. CS49531x DSP Memory Sizes
Memory
Type
DSP A
DSP B
X
16K SRAM, 16K ROM
10K SRAM, 8K ROM
Y
24K SRAM, 32K ROM
16K SRAM, 16K ROM
P
8K SRAM, 32K ROM
8K SRAM, 24K ROM
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CS495314-DVZR | 功能描述:音頻 DSP IC Multi-Channel Audio DSP Decoder RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風格: 封裝 / 箱體: 封裝:Tube |
| CS4953-CL | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:NTSC/PAL Digital Video Encoder |
| CS4953-CQ | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:NTSC/PAL Digital Video Encoder |
| CS4953XX | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:32-bit Audio Decoder DSP Family with Dual DSP Engine Technology |
| CS4953XX_08 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:32-bit Audio Decoder DSP Family |
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