參數(shù)資料
型號: CS495314-DVZ
廠商: Cirrus Logic Inc
文件頁數(shù): 6/19頁
文件大?。?/td> 0K
描述: IC DSP DECODER 32BIT 128-LQFP
標準包裝: 72
系列: *
其它名稱: 598-1944
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
DS705F2
14
5.10 Switching Characteristics — Serial Control Port - SPI Slave Mode
Parameter
Symbol
Min
Typical
Max
Units
SCP_CLK frequency1,2
1. The specification fspisck indicates the maximum speed of the hardware. The system designer should be aware that
the actual maximum speed of the communication port may be limited by the firmware application. Flow control using
the SCP_BSY pin should be implemented to prevent overflow of the input data buffer. At boot the maximum speed
is Fxtal/3.
2. When SCP1 is in SPI slave mode, very slow rise and fall times of the SCP_CLK edges may make the edges of the
SCP_CLK more susceptible to noise, resulting in non-smooth edges. Any glitch at the threshold levels of the SCP
port input signals could result in abnormal operation of the port.
In systems that have noise coupling onto SCP_CLK, slow rise and fall times may cause host communication
problems. Increasing rise time makes host communication more reliable.
fspisck
——
25
MHz
SCP_CS falling to SCP_CLK rising2
tspicss
24
ns
SCP_CLK low time2
tspickl
20
ns
SCP_CLK high time2
tspickh
20
ns
Setup time SCP_MOSI input
tspidsu
5—
ns
Hold time SCP_MOSI input
tspidh
5—
ns
SCP_CLK low to SCP_MISO output valid2
tspidov
——
11
ns
SCP_CLK falling to SCP_IRQ rising2
tspiirqh
20
ns
SCP_CS rising to SCP_IRQ falling2
tspiirql
0—
ns
SCP_CLK low to SCP_CS rising2
tspicsh
24
ns
SCP_CS rising to SCP_MISO output high-Z
tspicsdz
—20
ns
SCP_CLK rising to SCP_BSY falling2
tspicbsyl
—3*DCLKP+20
ns
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