參數(shù)資料
型號: CS495314-DVZR
廠商: CIRRUS LOGIC INC
元件分類: 顏色信號轉(zhuǎn)換
中文描述: COLOR SIGNAL DECODER, PQFP128
封裝: LEAD FREE, LQFP-128
文件頁數(shù): 10/35頁
文件大?。?/td> 295K
代理商: CS495314-DVZR
CS4953xx Data Sheet
32-bit Audio Decoder DSP Family
DS705PP8
18
5.14 Switching Characteristics — Parallel Control Port - Intel Slave Mode
Parameter
Symbol Min
Typical
Max
Unit
Address setup before PCP_CS and PCP_RD low or PCP_CS and
PCP_WR low
tias
5—
ns
Address hold time after PCP_CS and PCP_RD low or PCP_CS and
PCP_WR high
tiah
5—
ns
Read
Delay between PCP_RD then PCP_CS low or PCP_CS then
PCP_RD low
ticdr
0—
ns
Data valid after PCP_CS and PCP_RD low
tidd
18
ns
PCP_CS and PCP_RD low for read
tirpw
24
ns
Data hold time after PCP_CS or PCP_RD high
tidhr
8—
ns
Data high-Z after PCP_CS or PCP_RD high
tidis
18
ns
PCP_CS or PCP_RD high to PCP_CS and PCP_RD low for next
read1
1. The system designer should be aware that the actual maximum speed of the communication port may be limited by
the firmware application. Hardware handshaking on the PCP_BSY pin/bit should be observed to prevent
overflowing the input data buffer. AN288 CS4953xx /CS497xxx Firmware User’s Manual should be consulted for
the firmware speed limitations.
tird
30
ns
PCP_CS or PCP_RD high to PCP_CS and PCP_WR low for next
tirdtw
30
ns
PCP_RD rising to PCP_IRQ rising
tirdirqhl
12
ns
Write
Delay between PCP_WR then PCP_CS low or PCP_CS then
PCP_WR low
ticdw
0—
ns
Data setup before PCP_CS or PCP_WR high
tidsu
8—
ns
PCP_CS and PCP_WR low for write
tiwpw
24
ns
Data hold after PCP_CS or PCP_WR high
tidhw
8—
ns
PCP_CS or PCP_WR high to PCP_CS and PCP_RD low for next
tiwtrd
30
ns
PCP_CS or PCP_WR high to PCP_CS and PCP_WR low for next
tiwd
30
ns
PCP_WR rising to PCP_BSY falling
tiwrbsyl
—2*DCLKP + 20
ns
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