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參數(shù)資料
| 型號(hào)： | CS51024ED16 |
| 廠商： | ZF Electronics Corporation |
| 英文描述： | Enhanced Current Mode PWM Controller |
| 中文描述： | 增強(qiáng)電流模式PWM控制器 |
| 文件頁(yè)數(shù)： | 6/9頁(yè) |
| 文件大?。?/td> | 170K |
| 代理商： | CS51024ED16 |
6
C
Circuit Description
Figure 2: Typical Waveforms
Powering the IC
The IC has two supply and two ground pins. V
C
and
PGnd pins provide high speed power drive for the exter-
nal power switch. V
CC
and LGnd pins power the control
portion of the IC. The internal logic monitors the supply
voltage, V
CC
. During abnormal operating conditions, the
output is held low. The CS51021/22/23/24 requires only
75μA of startup current.
Voltage Feedback
The output voltage is monitored via the V
FB
pin and is
compared with the internal 2.5V reference. The error
amplifier output minus one diode drop is divided by 3
and connected to the negative input of the PWM compara-
tor. The positive input of the PWM comparator is connect-
ed to the modified current sense signal. The oscillator
turns the external power switch on at the beginning of
each cycle. When current sense ramp voltage exceeds the
reference side of PWM comparator, the output stage latch-
es off. It is turned on again at the beginning of the next
oscillatorcycle.
Current Sense and Protection
The current is monitored at the I
SENSE
pin. The
CS51021/22/23/24 has leading edge blanking circuitry
that ignores the first 55ns of each switching period.
Blanking is disabled when V
FB
is less than 2V so that the
minimum on-time of the controller does not have an addi-
tional 55ns of delay time during fault conditions. For the
remaining portion of the switching period, the current
sense signal, combined with a fraction of the slope com-
pensation voltage, is applied to the positive input of the
PWM comparator where it is compared with the divided
by three error amplifier output voltage. The pulse-by-
pulse overcurrent protection threshold is set by the volt-
age at the I
SET
pin. This voltage is passed through the I
SET
Clampand appears at the non-inverting input of the PWM
comparator, limiting its dynamic range according to the
following formula:
Overcurrent Threshold= 0.8
×
V
I(SENSE)
+0.1V + 0.1 V
SLOPE
where
V
I(SENSE)
is voltage at the I
SENSE
pin
and
V
SLOPE
is voltage at the SLOPE pin.
During extreme overcurrent or short circuit conditions,
the slope of the current sense signal will become much
steeper than during normal operation. Due to loop propa-
gation delay, the sensed signal will overshoot the pulse-
by-pulse threshold eventually reaching the second over-
current protection threshold which is 1.33 times higher
than the first threshold and is described by the following
equation:
2nd Threshold = 1.33
×
V
I(SET)
Exceeding the second threshold will reset the Soft Start
capacitor C
SS
and reinitiate the Soft Start sequence, repeat-
ing for as long as the fault condition persists.
Soft Start
During power up, when the output filter capacitor is dis-
charged and the output voltage is low, the voltage across
the Soft Start capacitor (V
SS
) controls the duty cycle. An
internal current source of 55μA charges C
SS
. The maxi-
mum error amplifier output voltage is clamped by the SS
Clamp. When the Soft Start capacitor voltage exceeds the
error amplifier output voltage, the feedback loop takes
over the duty cycle control. The Soft Start time can be esti-
mated with the following formula:
t
SS
= 9
×
10
4
×
C
SS
The Soft Start voltage, V
SS
, charges and discharges
between 0.25V and 4.7V.
Slope Compensation
DC-DC converters with current mode control require a
current sense signal with slope compensation to avoid
instability at duty cycles greater than 50%. Slope capacitor
C
S
is charged by an internal 53μA current source and is
discharged during the oscillator discharge time. The slope
compensation voltage is divided by 10 and is added to the
current sense voltage, V
I(SENSE)
. The signal applied to the
Theory of Operation
4.3V
200ns
0V
T
CH
T
DIS
V
IN
0V
0V
0V
V
SLOPE
IS + 0.1 SLOPE
IS
55ns Blanking
PWM COMP
SLOPE
R
T
C
T
SYNC
IS
V
DS
0V
0V
GATE
V
COMP
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|---|---|
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